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high speed oversampling cmos adc with 16-bit resolution at a 2.5 mhz output word rate ad9260 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features monolithic 16-bit, oversampled a/d converter 8 oversampli ng mode, 20 m s ps clock 2.5 mhz output word rate 1.01 mh z signa l passband wit h 0.004 db ripple signal-to-noise ratio: 88.5 db total harmonic distortion: C96 db spurious-free dynamic range : 100 db input referred noise: 0.6 lsb selectable ove r sampling rati o: 1, 2, 4, 8 selectable power dissipation: 150 mw to 585 mw 85 db stop-ban d atten u ation 0.004 db pass- band ripple linear phase single 5 v anal og supply, 5 v/ 3 v digital s u p p ly synchronize capability for par a llel adc interf ace twos complem e nt ou tpu t data 44-lea d mqfp produc t d e scripti o n the ad9260 is a 16-b i t, hig h -sp eed o v ers a m p l e d a n alog-t o - dig i t a l con v er te r (ad c ) t h a t o f fers excep t io na l d y na mic r a n g e o v er a wide band wid t h. th e ad9260 is ma n u f a c t ur ed on a n a d v a nc e d c m o s pro c e s s . hi g h dy n a m i c r a nge i s a c h i e v e d w i t h a n o v ers a m p ling ra t i o o f 8 t h r o ug h t h e us e o f a p r o p r i et a r y t e chni q u e t h a t c o m b i n es t h e adva n t a g es o f sig m a-de l t a and p i p e lin e con v er ter t e c h n o log i es. the ad9260 is a swi t ch e d - ca p a ci t o r ad c wi th a n o minal f u l l -s cale in p u t ra n g e o f 4 v . i t of f e r s a d i f f e r e n t i a l i n put w i t h 6 0 d b of c o m m on - m o d e re j e c - tio n o f co mm on-m o d e sig n als. the sig n al ra n g e o f e a c h dif f er - en t i al in p u t is 1 v cen t er e d o n a 2.0 v co mm on-m o d e leve l . the o n -chi p de cima t i on f i l t er i s co nf igur e d fo r max i m u m p e r f o r ma n c e and f l exi b i l i t y . a s e r i es o f t h r e e ha lf-b an d fir f i lte r st age s prov i d e 8 d e c i m a t i on f i lte r i n g w i t h 8 5 d b of stop - ba nd a t t e n u a t ion an d 0.004 db o f p a s s -ba nd r i p p l e . an o n bo a r d dig i tal m u l t i p le xer al lo ws th e u s er t o acces s da t a f r o m th e va r i o u s s t a g es of t h e de cima t i on f i l t er . th e on- c hi p p r og ra mma b l e r e fer e n c e an d r e fer e n c e b u f f er a m plif ier a r e co nf igur e d fo r max i m u m acc u rac y a n d f l ex i b i l i t y . a n ex ter n a l r e fer e n c e can als o b e ch os e n t o s u i t t h e us er s sp e c if ic dc acc u r a c y a n d dr if t r e q u ir e m e n ts . the ad9260 op era t es o n a sin g l e +5 v s u p p l y , typ i cal l y co n s umin g 585 mw o f p o w e r . a p o w e r s c al in g cir c ui t is p r o v ided al lo win g t h e ad9260 t o o p era t e a t p o w e r co n s um p - func ti on a l bl ock di a g r a m multibit sigma-delta modulator av dd a vss reset/ sync 12-bit: 20mhz digital demodulator stage 1:2x decimation filter stage 2:2x decimation filter stage 3:2x decimation filter ou tpu t m o d e m u ltiplexer outp ut re gis t e r drv dd d r vss dvss dvdd 16-bit: 10mhz 16-bit: 5mhz 16-bit: 2.5mhz av dd a vss av dd a vss mode register reference buffer bandgap reference bias circuit clock buffer ad9260 otr bit1? bit16 dav cs mode clk bias adjust refcom sense vref common mode ref bottom ref top vinb vina read 00581-c-001 fi g u r e 1 . tio n leve ls as lo w as 150 mw a t r e d u ced c l o c k and da t a ra t e s. the ad9260 is a v a i la b l e in a 44 -lead m q fp p a c k a g e and is s p e c if ie d t o o p e r a t e o v er t h e i n d u s t r i al t e m p er a t ur e ra n g e . produc t h i ghligh ts the ad9260 is fa b r ic a t e d o n a v e r y cos t ef f e c t i v e cm os p r o c es s. h i g h sp e e d , p r e c isio n, mixe d-sig n al analog cir c ui ts a r e co m b in e d wi t h hig h den s i t y dig i tal f i l t er cir c u i ts. th e ad9260 o f f e rs a co m p let e sin g le-c hi p 16 -b i t s a m p l i n g ad c wi t h a 2.5 mh z o u t p ut da t a ra t e in a 44-le ad mqfp . s e le cta b le i n t e r n al d e cim a t i o n f i l t e r in g th e ad9260 p r o v ides a hig h p e r f o r ma n c e de cima tion f i l t er wi th 0.004 db p a ss-b an d r i p p l e a nd 85 db o f sto p -b and a t te n u a t io n. t h e f i l t er is co nf igura b le wi th o p t i o n s f o r 1, 2, 4, a n d 8 decima t i o n . po w e r s c a l i n g the ad9260 co n s u m es a lo w 585 mw o f p o w e r a t 16 -b i t r e s o l u tio n an d 2.5 mh z o u t p u t da ta ra t e . i t s p o w e r can be s c aled do wn t o as lo w as 150 mw a t r e d u ce d cl o c k r a tes . si ng l e su pp l y b o t h t h e ana l o g a n d dig i t a l p o r t io n s o f t h e ad9260 can o p era t e o f f o f a sing le +5 v s u p p l y , sim p lif y in g sys t em p o w e r su p p l y desig n . th e dig i tal log i c wil l als o acco mm o d a t e a sin g le +3 v s u p p l y f o r r e d u ced p o w e r .
ad9260 rev. c | page 2 of 44 table of contents specifications ..................................................................................... 3 clock input frequency range .................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital filter characteristics ....................................................... 6 digital filter characteristics ....................................................... 7 digital specifications ................................................................... 9 switching specifications ............................................................ 10 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 ter mi nolo g y .................................................................................... 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 14 typical ac characterization curves vs. decimation mode ................................................................. 15 typical ac characterization curves for 8 mode ................ 16 typical ac characterization curves for 4 mode ................ 17 typical ac characterization curves for 2 mode ................ 18 typical ac characterization curves for 1 mode ................ 19 typical ac characterization curves ....................................... 20 additional ac characterization curves ................................. 21 theory of operation ...................................................................... 23 analog input and reference overview ....................................... 24 input span ................................................................................... 24 input compliance range ........................................................... 24 analog input operation ............................................................ 24 driving the input ........................................................................ 25 reference operation ...................................................................... 28 digital inputs and outputs ........................................................... 30 digital outputs ........................................................................... 30 mode operation ......................................................................... 31 bias pin operation ..................................................................... 32 power dissipation considerations ............................................... 33 digital output driver considerations (drvdd) ................. 33 grounding and decoupling ...................................................... 34 evaluation board general description ....................................... 36 features and user controls ....................................................... 36 shipment configuration ............................................................ 37 quick setup ................................................................................. 37 application information ........................................................... 38 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43 revision history 7/04changed from rev. b to rev. c changed trimpot to variable resistor ..................... universal updated format................................................................ universal updated outline dimensions ......................................................43 changes to ordering guide .........................................................43 5/00changed from rev. a to rev. b. 1/98changed from rev. 0 to rev. a.
ad9260 rev. c | page 3 of 44 specifications clock input frequency range table 1. parameterdecimation factor (n) ad9260 (8) ad9260 (4) ad9260 (2) ad9260 (1) unit clock input (modulator sample rate, f clock ) 1 1 1 1 khz min 20 20 20 20 mhz max output word rate (fs = f clock /n) 0.125 0.250 0.500 1 khz min 2.5 5 10 20 mhz max dc specifications avdd = +5 v, dvdd = +3 v, drvdd = +3 v, f clock = 20 msps, v ref = +2.5 v, input cml = 2.0 v t min to t max unless otherwise noted, r bias = 2 k?. table 2. parameterdecimation factor (n) ad9260 (8) ad9260 (4) ad9260 (2) ad9260 (1) unit resolution 16 16 16 12 bits min input referred noise (typ) 1.0 v reference 1.40 2.4 6.0 1.3 lsb rms typ 2.5 v reference 1 0.68 (90.6) 1.2 (86) 3.7 (76) 1.0 (63.2) lsb rms typ (db typ) accuracy integral nonlinearity (inl) 0.75 0.75 0.75 0.3 lsb typ differential nonlinearity (dnl) 0.50 0.50 0.50 0.25 lsb typ no missing codes 16 16 16 12 bits guaranteed offset error 0.9 (0.5) (0.5) (0.5) (0.5) % fsr max (typ @ +25c) gain error 2 2.75 (0.66) (0.66) (0.66) (0.66) % fsr max (typ @ +25c) gain error 3 1.35 (0.7) (0.7) (0.7) (0.7) % fsr max (typ @ +25c) temperature drift offset error 2.5 2.5 2.5 2.5 ppm/c typ gain error 2 22 22 22 22 ppm/c typ gain error 3 7.0 7.0 7.0 7.0 ppm/c typ power supply rejection avdd, dvdd, drvdd (+5 v 0.25 v) 0.06 0.06 0.06 0.06 % fsr max analog input i n p u t s p a n v ref = 1.0 v 1.6 1.6 1.6 1.6 v p p diff. max v ref = 2.5 v 4.0 4.0 4.0 4.0 v p p diff. max input (vina or vinb) range +0.5 +0.5 +0.5 +0.5 v min +avdd C0.5 +avdd C0.5 +avdd C0.5 +avdd C0.5 v max input capacitance 10.2 10.2 10.2 10.2 pf typ internal voltage reference output voltage (1 v mode) 1 1 1 1 v typ output voltage error (1 v mode) 14 14 14 14 mv max output voltage (2.5 v mode) 2. 5 2.5 2.5 2.5 v typ output voltage error (2.5 v mode) 35 35 35 35 mv max load regulation 4 1 v ref 0.5 0.5 0.5 0.5 mv max 2.5 v ref 2.0 2.0 2.0 2.0 mv max reference input resistance 8 8 8 8 k? power supplies s u p p l y v o l t a g e s avdd +5 +5 +5 +5 v ( 5%)
ad9260 rev. c | page 4 of 44 parameterdecimation factor (n) ad9260 (8) ad9260 (4) ad9260 (2) ad9260 (1) unit dvdd and drvdd +5.5 +5.5 +5.5 +5.5 v max +2.7 +2.7 +2.7 +2.7 v min s u p p l y c u r r e n t iavdd 115 115 115 115 ma typ 134 ma max idvdd 12.5 10.3 6.5 2.4 ma typ 3.5 ma max idrvdd 0.450 0.850 1.7 2.6 ma typ power consumption 613 608 600 585 mw typ 630 mw max 1 vina and vinb connect to dut cml. 2 including internal 2.5 v reference. 3 excluding internal 2.5 v reference. 4 load regulation with 1 ma load current (in addition to that required by ad9260). ac specifications avdd = +5 v, dvdd = +3 v, drvdd = +3 v, f clock = 20 msps, v ref = +2.5 v, input cml = 2.0 v t min to t max unless otherwise noted, r bias = 2 k?. table 3. parameterdecimation factor (n) ad9260(8) ad9260(4) ad9260(2) ad9260(1) unit dynamic performance input test frequency: 100 khz (typ) signal-to-noise ratio (snr) input amplitude = C0.5 dbfs 88.5 82 74 63 db typ input amplitude = C6.0 dbfs 82.5 78 68 58 db typ snr and distortion (sinad) input amplitude = C0.5 dbfs 87.5 82 74 63 db typ input amplitude = C6.0 dbfs 82 77.5 69 58 db typ total harmonic distortion (thd) input amplitude = C0.5 dbfs C96 C96 C97 C98 db typ input amplitude = C6.0 dbfs C93 C98 C96 C98 db typ spurious-free dynamic range (sfdr) input amplitude = C0.5 dbfs 100 98 98 88 db typ input amplitude = C6.0 dbfs 94 100 94 84 db typ input test frequency: 500 khz signal to noise ratio (snr) input amplitude = C0.5 dbfs 86.5 82 74 63 db typ 80.5 db min input amplitude = C6.0 dbfs 82.5 77 68 58 db typ snr and distortion (sinad) input amplitude = C0.5 dbfs 86.0 81 74 63 db typ 80.0 db min input amplitude = C6.0 dbfs 82.0 77 68 58 db typ total harmonic distortion (thd) input amplitude = C0.5 dbfs C 97.0 C92 C89 C86 db typ C90.0 db max input amplitude = C6.0 dbfs C 95.5 C96 C89 C86 db typ spurious-free dynamic range (sfdr) input amplitude = C0.5 dbfs 99.0 92 91 88 db typ 90.0 db max
ad9260 rev. c | page 5 of 44 parameterdecimation factor (n) ad9260(8) ad9260(4) ad9260(2) ad9260(1) unit input amplitude = C6.0 dbfs 98 100 91 82 db typ input test frequency: 1.0 mhz (typ) signal-to-noise ratio (snr) input amplitude = C0.5 dbfs 85 82 74 63 db typ input amplitude = C6.0 dbfs 80 76 68 58 db typ snr and distortion (sinad) input amplitude = C0.5 dbfs 84.5 81 74 63 db typ input amplitude = C6.0 dbfs 80 76 69 58 db typ total harmonic distortion (thd) input amplitude = C0.5 dbfs C102 C96 C82 C79 db typ input amplitude = C6.0 dbfs C96 C94 C84 C77 db typ spurious-free dynamic range (sfdr) input amplitude = C0.5 dbfs 105 98 83 80 db typ input amplitude = C6.0 dbfs 98 96 87 80 db typ input test frequency: 2.0 mhz (typ) signal-to-noise ratio (snr) input amplitude = C0.5 dbfs 82 74 63 db typ input amplitude = C6.0 dbfs 76 68 58 db typ snr and distortion (sinad) input amplitude = C0.5 dbfs 81 73 62 db typ input amplitude = C6.0 dbfs 76 69 58 db typ total harmonic distortion (thd) input amplitude = C0.5 dbfs C101 C80 C75 db typ input amplitude = C6.0 dbfs C95 C80 C76 db typ spurious-free dynamic range (sfdr) input amplitude = C0.5 dbfs 104 80 78 db typ input amplitude = C6.0 dbfs 100 83 79 db typ input test frequency: 5.0 mhz (typ) signal-to-noise ratio (snr) input amplitude = C0.5 dbfs 59 db typ input amplitude = C6.0 dbfs 57 db typ snr and distortion (sinad) input amplitude = C0.5 dbfs 58 db typ input amplitude = C6.0 dbfs 57 db typ total harmonic distortion (thd) input amplitude = C0.5 dbfs C58 db typ input amplitude = C6.0 dbfs C67 db typ spurious-free dynamic range (sfdr) input amplitude = C0.5 dbfs 59 db typ input amplitude = C6.0 dbfs 70 db typ intermodulation distortion f in 1 = 475 khz, f in 2 = 525 khz C93 C91 C91 C83 dbfs typ f in 1 = 950 khz, f in 2 = 1.050 mhz C95 C86 C85 C83 dbfs typ dynamic characteristics full power bandwidth 75 75 75 75 mhz typ small signal bandwidth (a in = C20 dbfs) 75 75 75 75 mhz typ aperture jitter 2 2 2 2 ps rms typ
ad9260 rev. c | page 6 of 44 digital filter characteristics table 4. parameter ad9260 unit 8 decimation (n = 8) pass-band ripple 0.00125 db max stop-band attenuation 82.5 db min pass-band 0 mhz min 0.605 (f clock /20 mhz) mhz max stop-band 1.870 (f clock /20 mhz) mhz min 18.130 (f clock /20 mhz) mhz max pass-band/transition band frequency (C0.1 db point) 0.807 (f clock /20 mhz) mhz max (C3.0 db point) 1.136 (f clock /20 mhz) mhz max absolute group delay 1 13.55 (20 mhz/f clock ) s max group delay variation 0 s max settling time (to 0.0007%) 1 24.2 (20 mhz/f clock ) s max 4 decimation (n = 4) pass-band ripple 0.001 db max stop-band attenuation 82.5 db min pass-band 0 mhz min 1.24 (f clock /20 mhz) mhz max stop-band 3.75 (f clock /20 mhz) mhz min 16.25 (f clock /20 mhz) mhz max pass-band/transition band frequency (C0.1 db point) 1.61 (f clock /20 mhz) mhz max (C3.0 db point) 2.272 (f clock /20 mhz) mhz max absolute group delay 1 2.90 (20 mhz/f clock ) s max group delay variation 0 s max settling time (to 0.0007%) 1 5.05 (20 mhz/f clock ) s max 2 decimation (n = 2) pass-band ripple 0.0005 db max stop-band attenuation 85.5 db min pass-band 0 mhz min 2.491 (f clock /20 mhz) mhz max stop-band 7.519 (f clock /20 mhz) mhz min 12.481 (f clock /20 mhz) mhz max pass-band/transition band frequency (C0.1 db point) 3.231 (f clock /20 mhz) mhz max (C3.0 db point) 4.535 (f clock /20 mhz) mhz max absolute group delay 1 0.80 (20 mhz/f clock ) s max group delay variation 0 s max settling time (to 0.0007%) 1 1.40 (20 mhz/f clock ) s max 1 decimation (n = 1) propagation delay: t prop 13 ns max absolute group delay (225 (20 mhz/f clock )) + t prop ns max 1 to determine overall absolute group delay and/or settling time inclusive of delay from the sigma-delta modulator, add absolute group delay and/or settling time pertaining to specific decimation mode to the absolute group delay specified in 1 decimation.
ad9260 r e v. c | pa ge 7 o f 4 4 digi tal fil t er chara c teristics ?120 ?100 ?80 ?60 ?40 ?20 0 magnitude (db) 0.4 0.6 0 0.2 0.8 1.0 1.2 frequency (normalized to ) 00581-c-002 f i g u re 2. 8x fir f i lt er f r equ e nc y r e s p o n s e ?120 ?100 ?80 ?60 ?40 ?20 0 magnitude (db) 0.4 0.6 0 0.2 0.8 1.0 1.2 frequency (normalized to ) 00581-c-003 f i g u re 3. 4x fir f i lt er f r equ e nc y r e s p o n s e ?120 ?100 ?80 ?60 ?40 ?20 0 magnitude (db) 0.4 0.6 0 0.2 0.8 1.0 1.2 frequency (normalized to ) 00581-c-004 f i g u re 4. 2x fir f i lt er f r equ e nc y r e s p o n s e ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 n o r m a l ized ou tpu t r espon s e 200 300 0 100 400 500 600 clock periods (relative to clk) 00581-c-005 f i g u re 5. 8x fir f i lt er i m puls e r e s p o n s e ?0.2 0 0.2 0.4 0.6 0.8 1.0 n o r m a l ized ou tpu t r espon s e clock periods (relative to clk) 0 1 0 2 03 04 05 0 6 0 7 08 09 0 1 0 0 1 1 0 00581-c-006 f i g u re 6. 4x fir f i lt er i m puls e r e s p o n s e ?0.2 0 0.2 0.4 0.6 0.8 1.0 n o r m a l ized ou tpu t r espon s e 0 5 10 15 20 25 clock periods (relative to clk) 00581-c-007 f i g u re 7. 2x fir f i lt er i m puls e r e s p o n s e
ad9260 rev. c | page 8 of 44 table 5. integer filter coefficients for first stage decimation filter (23-tap half-band fir filter) lower coefficient upper coefficient integer value h(1) h(23) C1 h(2) h(22) 0 h(3) h(21) 13 h(4) h(20) 0 h(5) h(19) C66 h(6) h(18) 0 h(7) h(17) 224 h(8) h(16) 0 h(9) h(15) C642 h(10) h(14) 0 h(11) h(13) 2496 h(12) 4048 table 6. integer filter coefficients for second stage decimation filter (43-tap half-band fir filter) lower coefficient upper coefficient integer value h(1) h(43) 3 h(2) h(42) 0 h(3) h(41) C12 h(4) h(40) 0 h(5) h(39) 35 h(6) h(38) 0 h(7) h(37) C83 h(8) h(36) 0 h(9) h(35) 172 h(10) h(34) 0 h(11) h(33) C324 h(12) h(32) 0 h(13) h(31) 572 h(14) h(30) 0 h(15) h(29) C976 h(16) h(28) 0 h(17) h(27) 1680 h(18) h(26) 0 h(19) h(25) C3204 h(20) h(24) 0 h(21) h(23) 10274 h(22) 16274 note: the composite filter undecimated coefficients (i.e., impulse response) in the 4 decimation mode can be determined by convolving the first stage filter taps with a zero stuffed version of the second stage filter taps (i.e., insert one zero between samples). similarly, the composite filter coefficients in the 8 decimation mode can be determined by convolving the taps of the composite 4 decimation mode (as previously determined) with a zero stuffed version of the third stage filter taps (i.e., insert three zeros between samples). table 7. integer filter coefficients for third stage decimation filter (107-tap half-band fir filter) lower coefficient upper coefficient integer value h(1) h(107) C1 h(2) h(106) 0 h(3) h(105) 2 h(4) h(104) 0 h(5) h(103) C2 h(6) h(102) 0 h(7) h(101) 3 h(8) h(100) 0 h(9) h(99) C3 h(10) h(98) 0 h(11) h(97) 1 h(12) h(96) 0 h(13) h(95) 3 h(14) h(94) 0 h(15) h(93) C12 h(16) h(92) 0 h(17) h(91) 27 h(18) h(90) 0 h(19) h(89) C50 h(20) h(88) 0 h(21) h(87) 85 h(22) h(86) 0 h(23) h(85) C135 h(24) h(84) 0 h(25) h(83) 204 h(26) h(82) 0 h(27) h(81) C297 h(28) h(80) 0 h(29) h(79) 420 h(30) h(78) 0 h(31) h(77) C579 h(32) h(76) 0 h(33) h(75) 784 h(34) h(74) 0 h(35) h(73) C1044 h(36) h(72) 0 h(37) h(71) 1376 h(38) h(70) 0 h(39) h(69) C1797 h(40) h(68) 0 h(41) h(67) 2344 h(42) h(66) 0 h(43) h(65) C3072 h(44) h(64) 0 h(45) h(63) 4089 h(46) h(62) 0 h(47) h(61) C5624 h(48) h(60) 0 h(49) h(59) 8280 h(50) h(58) 0 h(51) h(57) C14268 h(52) h(56) 0 h(53) h(55) 43520 h(54) 68508
ad9260 r e v. c | pa ge 9 o f 4 4 digi tal spe c ific ati o ns a v d d = +5 v , d v d d = +5 v , t min to t max un les s o t h e r w is e no t e d . table 8. parameter ad9260 unit clock 1 and logic inpu ts high level input voltage ( d vdd = +5 v) +3.5 v min ( d vdd = +3 v) +2.1 v max low level input voltage ( d vdd = +5 v) +1.0 v min ( d vdd = +3 v) +0.9 v max high level input current (v in = dvdd) 10 a max low level input current (v in = 0 v) 10 a max input capacitance 5 pf typ logic output s (with drvdd = 5 v) high level output voltage (i oh = 50 a) +4.5 v min high level output voltage (i oh = 0.5 ma) +2.4 v min low level outp ut voltage 2 (i ol = 0.3 ma) +0.4 v max low level outp ut voltage (i ol = 50 a) +0.1 v max output capacitance 5 pf typ logic output s (with drvdd = 3 v) high level output voltage (i oh = 50 a) +2.4 v min low level outp ut voltage (i ol = 50 a) +0.7 v max 1 si n c e clk i s r e f e re n c ed t o avd d , +5 v lo gi c i n put leve ls o n ly a pply. 2 the ad9260 is not guaranteed to m e et v ol = 0.4 v m a x fo r st a n da rd ttl l o a d of i ol = 1.6 m a . analog input input clock data output dav s1 s2 t ds t h t ch t cl t dav t di t c read cs t od t oe 00581-c-008 f i g u re 8. ti ming d i ag r a m
ad9260 rev. c | page 10 of 44 input clock reset dav t res-dav t clk-dav 00581-c-009 fi g u r e 9 . reset ti mi ng d i ag r a m switchi n g specificati o ns a v d d = +5 v , d v d d = +5 v , c l = 20 pf , t min to t max unles s o t h e r w is e n o t e d. table 9. parameters symbol ad9260 unit clock peri od t c 50 ns min data available (dav) period t dav t c mode ns min data invalid t di 40% t dav ns max data set-up time t ds t dav Ct h Ct di ns min clock pulse-width high t ch 22.5 ns min clock pulse-width low t cl 22.5 ns min data hold time t h 3.5 ns min reset to dav delay t resC dav 10 ns typ clock to dav delay t clk C dav 15 ns typ three-state output disable tim e t od 8 ns typ three-state output enable time t oe 45 ns typ
ad9260 rev. c | page 11 of 44 absolute maximum ratings table 10. parameter rating avdd to a v ss C0.3 v to +6.5 v dvdd to dv ss C0.3 v to +6.5 v avss to dvss C0.3 v to +0.3 v avdd to d v dd C6.5 v to +6.5 v drvdd to d rvs s C0.3 v to +6.5 v drvss to a v ss C0.3 v to +0.3 v refcom to avs s C0.3 v to +0.3 v clk, mode, read, cs , and reset to dvss C0.3 v to dv dd + 0.3 v digital outputs to drvss C0.3 v to dr vd d + 0.3 v vina, v i nb, cml , and bias to av ss C0.3 v to av dd + 0.3 v vref to a v ss C0.3 v to avdd + 0.3 v sense to a v ss C0.3 v to avdd + 0.3 v capb and capt to avss C0.3 v to av dd + 0.3 v junction tempe r ature 150c storage temperature C65c to +150c lead temperature (10 s) 300c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n s o f t h is sp e c if ic a t ion is n o t im pli e d . e x p o sur e t o a b s o l u te max i m u m ra t i n g s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . thermal c h aracteristics ther ma l resist a n ce 44-l e ad m q fp ja = 53.2c/w jc = 19c/w esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9260 rev. c | page 12 of 44 terminology integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. note: conventional inl and dnl measurements dont really apply to ? converters: the dnl looks continually better if longer data records are taken. for the ad9260, inl and dnl numbers are given as representative. zero error the major carry transition should occur for an analog value 1/2 lsb below vina = vinb. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference and the ideal difference between first and last code transitions. temp er atu re d r i f t the temperature drift for zero error and gain error specifies the maximum change from the initial (+25c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, it is possible to get a measure of performance expressed as n , the effective number of bits: n = ( sinad ? 1.76)/6.02 thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale).
ad9260 rev. c | page 13 of 44 pin conf iguration and fu nction descriptions pin 1 identifier top view (not to scale) ad9260 1 2 1 3 14 15 16 1 7 18 1 9 2 0 21 2 2 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 3 5 3 4 37 29 30 31 32 27 28 25 26 23 24 33 refcom vref sense reset avss avdd cs dvss avss dvdd avdd drvss drvdd clk read (lsb) bit16 bit15 bit14 dav otr bit1 (msb) bit2 bit1 3 bit1 2 av dd nc vin b vin a nc cm l av s s bit8 cap t cap b bias bit1 1 mo de bit1 0 bit9 bit7 bit6 bit5 bit4 bit3 nc = no connect 00581-c-010 f i gur e 1 0 . p i n c o nfigur a t io n ta ble 11. pi n f u nct i on des c ri pt i o ns pin no. mnemonic description 1 dvss digital ground. 2, 29, 38 avss analog ground. 3 dvdd +3 v to +5 v dig i tal supply. 4, 28, 44 avdd +5 v analog supply. 5 drvss digital output driver ground. 6 drvdd +3 v to +5 v dig i tal output driv er supply. 7 clk clock in put. 8 read part of dsp inter f ace pull low to disable output bits. 9 bit16 least significant data bit (lsb). 10C23 bit15Cbit2 data output bit. 24 bit1 most significant data bit (msb). 25 ot r out of rangeset when conv erter or filter ov erflow s. 26 dav data available. 27 cs chip select (cs): active low. 30 reset reset : active low. 31 sense reference amplifier sense: selects ref level. 32 vref input span sele ct reference i/o. 33 refcom reference com m on. 34 mode mode sel e ctsel ects decimation mode. 35 bias power bias. 36 capb noise reduction pindecouples reference level. 37 capt noise reduction pindecouples reference level. 39 cml common-mode level (avdd/2.5). 40, 43 nc no connect (groun d for shielding purposes). 41 vina analog input pin (+). 42 vinb analog input pin (C).
ad9260 rev. c | page 14 of 44 typical perf orm ance cha r acte ristics a v d d = d v dd = d r vd d = +5.0 v , 4 v i n p u t s p a n , dif f er en t i al d c c o u p led i n p u t wi t h cml = 2.0 v , f cl o c k = 20 ms ps, f u l l b i as. ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 db below full scale 0.4 0.6 0 0.2 0.8 1.0 1.2 frequency (mhz) 00581-c-011 100khz input 20mhz clock 8 decimation thd: ?96db f i gur e 1 1 . sp e c tr al p l o t o f the ad9 260 a t 10 0 khz input, 20 mh z clo c k , 8x osr (2. 5 m h z o u tput d a t a rate) ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 db below full scale 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) 00581-c-012 100khz input 20mhz clock 4 decimation thd: ?98db f i gur e 1 2 . sp e c tr al p l o t o f the ad9 260 a t 10 0 khz input, 20 mh z clo c k , 4x osr (5 mh z o u tput d a t a rate) ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 db below full scale 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 frequency (mhz) 00581-c-013 100khz input 20mhz clock 2 decimation thd: ?98db f i gur e 1 3 . sp e c tr al p l o t o f the ad9 260 a t 10 0 khz input, 20 mh z clo c k , 2x osr (1 0 m h z o u tput d a ta rate) ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 db below full scale 0 1 23 45 6 7 8 9 1 0 frequency (mhz) 00581-c-014 100khz input 20mhz clock 1 decimation thd: ?98db f i gur e 1 4 . sp e c tr al p l o t o f the ad9 260 a t 10 0 khz input, 20 mh z clo c k , u n d eci m a ted ( 2 0 m h z o u t p ut d a t a rate) 90 94 98 102 106 110 wors t cas e s p ur (dbfs ) 0 0.2 0.4 0.6 0.8 1.0 frequency (mhz) 00581-c-015 ?12dbfs/tone ?26dbfs/tone ?46dbfs/tone ?6.5dbfs/tone f i gure 15. d u al- t o n e sfdr v s . input f r equ e nc y (f 1 = f 2 , s p an = 10% center fr e q u e n c y , m o d e = 8 x ) ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 db below full scale 0.4 0.6 0 0.2 0.8 1.0 1.2 frequency (mhz) 00581-c-016 dual-tone test f1 = 1.0mhz f2 = 975khz 20mhz clock 8 decimation im3: ?94db f i gur e 1 6 . t w o - t o ne sp e c t r al p e r f o r ma nc e o f the ad9260 gi v e n inputs a t 97 5 k h z and 1.0 m h z, 20 m h z cl ock , 8x d e c i m a t i on
ad9260 rev. c | page 15 of 44 typical ac character i zation cu rves vs. de cimation mode a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , dif f er en tial d c c o u p led i n p u t wi t h cm l = 2 v , a in = 0. 5 db fs f u l l b i as. 50 55 60 65 70 75 s i nad (dbfs ) 80 85 90 input frequency (mhz) 0.1 1.0 10.0 00581-c-017 8 mode 4 mode 2 mode 1 mode f i gure 17. sinad vs. input f r eque nc y (f cl o c k = 20 ms ps) 8x sinad per f o r m a nce l i m it e d by no is e cont r i bu t i on of i n put dif f e r e nt ia l op a m p d r ive r ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 thd (dbfs ) input frequency (mhz) 0.1 1.0 10.0 00581-c-018 8 mode 4 mode 2 mode 1 mode fi g u r e 1 8 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 20 msp s ) ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 s f dr (dbfs ) input frequency (mhz) 0.1 1.0 10.0 00581-c-019 8 mode 4 mode 2 mode 1 mode fi g u r e 1 9 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 2 0 ms ps) 50 55 60 65 70 75 s i nad (dbfs ) 80 85 90 input frequency (mhz) 0.1 1.0 10.0 00581-c-020 8 mode 4 mode 2 mode 1 mode f i gure 20. sinad vs. input f r eque nc y (f cl o c k = 10 msp s ) ?120 ?115 ?110 ?105 ?100 ?9 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 thd (dbfs ) input frequency (mhz) 0.1 1.0 10.0 00581-c-021 8 mode 4 mode 2 mode 1 mode fi g u r e 2 1 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 10 msp s ) ?120 ?115 ?110 ?105 ?100 ?9 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 s f dr (dbfs ) input frequency (mhz) 0.1 1.0 10.0 00581-c-022 8 mode 4 mode 2 mode 1 mode fi g u r e 2 2 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 1 0 ms ps)
ad9260 rev. c | page 16 of 44 typical ac character i zation cu rves for 8 mode a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , dif f er en tial d c c o u p led i n p u t wi t h cm l = 2 v , f u ll b i as. 60 65 70 75 80 85 90 s i nad (db) input frequency (mhz) 0.1 1.0 00581-c-023 ?6.0dbfs ?0.5dbfs ?20dbfs f i gure 23. sinad vs. input f r eque nc y (f cl o c k = 20 ms ps) si nad p e r f or manc e li mi ted by n o is e co nt ribut i on of input differ e ntial op amp driv er . ?110 ?105 ?100 ?95 ?90 ?85 thd (db) ?80 ?75 ?70 input frequency (mhz) 0.1 1.0 00581-c-024 ?6.0dbfs ?0.5dbfs ? 20dbfs fi g u r e 2 4 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 20 msp s ) 80 85 90 95 100 105 s f dr (dbc ) input frequency (mhz) 0.1 1.0 00581-c-025 ? 6.0dbfs ? 0.5dbfs ? 20dbfs fi g u r e 2 5 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 2 0 ms ps) 60 65 70 75 80 85 90 s i nad (db) input frequency (mhz) 0.1 1.0 00581-c-026 ? 6.0dbfs ?0.5dbfs ? 20dbfs f i gure 26. sinad vs. input f r eque nc y (f cl o c k - = 10 ms ps) ? 105 ? 100 ?95 ?90 ?85 ?80 ?75 ?70 thd (db) input frequency (mhz) 0.1 1.0 00581-c-027 ? 6.0dbfs ?0.5dbfs ? 20dbfs fi g u r e 2 7 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 10 msp s ) 80 85 90 95 100 105 s f dr (dbc ) input frequency (mhz) 0.1 1.0 00581-c-028 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 2 8 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 1 0 ms ps)
ad9260 rev. c | page 17 of 44 typical ac character i zation cu rves for 4 mode a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , dif f er en tial d c c o u p led i n p u t wi t h cm l = 2 v , f u ll b i as. 50 55 60 65 70 75 s i nad (db) 80 85 90 input frequency (mhz) 0.1 1.0 10.0 00581-c-029 ?6.0dbfs ? 0.5dbfs ?20dbfs f i gure 29. sinad vs. input f r eque nc y (f cl o c k = 20 msp s ) ?110 ?105 ?100 ?95 ?90 ?85 thd (db) ?80 ?75 ?70 input frequency (mhz) 0.1 1.0 10.0 00581-c-030 ? 6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 3 0 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 20 msp s ) 80 85 90 95 100 105 110 s f dr (dbc ) input frequency (mhz) 0.1 1.0 10.0 00581-c-031 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 3 1 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 2 0 ms ps) 60 65 70 75 80 85 90 s i nad (db) input frequency (mhz) 0.1 1.0 00581-c-032 ? 6.0dbfs ? 0.5dbfs ? 20dbfs f i gure 32. sinad vs. input f r eque nc y (f cl o c k = 10 msp s ) ?110 ?105 ?100 ?95 ?90 ?85 thd (db) ?80 ?75 ?70 input frequency (mhz) 0.1 1.0 00581-c-033 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 3 3 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 10 msp s ) 80 85 90 95 100 105 110 s f dr (dbc ) input frequency (mhz) 0.1 1.0 00581-c-034 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 3 4 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 1 0 ms ps)
ad9260 rev. c | page 18 of 44 typical ac character i zation cu rves for 2 mode a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , dif f er en tial d c c o u p led i n p u t wi t h cm l = 2 v , f u ll b i as. 50 55 60 65 70 75 80 s i nad (db) input frequency (mhz) 0.1 1.0 10.0 00581-c-035 ?6.0dbfs ?0.5dbfs ?20dbfs f i gure 35. sinad vs. input f r eque nc y (f cl o c k = 20 msp s ) ?100 ?95 ?90 ?85 ?80 ?75 thd (db) ?70 ?65 ?60 input frequency (mhz) 0.1 1.0 10.0 00581-c-036 ?6.0dbfs ?0.5dbfs ? 20dbfs fi g u r e 3 6 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 20 msp s ) 70 75 80 85 90 95 100 s f dr (dbc ) input frequency (mhz) 0.1 1.0 10.0 00581-c-037 ?6.0dbfs ? 0.5dbfs ?20dbfs fi g u r e 3 7 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 2 0 ms ps) 50 55 60 65 70 75 80 s i nad (db) input frequency (mhz) 0.1 1.0 10.0 00581-c-038 ?6.0dbfs ? 0.5dbfs ?20dbfs f i gure 38. sinad vs. input f r eque nc y (f cl o c k = 10 msp s ) ?100 ?95 ?90 ?85 ?80 ?75 thd (db) ?70 ?65 ?60 input frequency (mhz) 0.1 1.0 10.0 00581-c-039 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 3 9 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 10 msp s ) 70 75 80 85 90 95 100 s f dr (dbc ) input frequency (mhz) 0.1 1.0 10.0 00581-c-040 ?6.0dbfs ? 0.5dbfs ?20dbfs fi g u r e 4 0 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 1 0 ms ps)
ad9260 rev. c | page 19 of 44 typical ac character i zation cu rves for 1 mode a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , dif f er en tial d c c o u p led i n p u t wi t h cm l = 2 v , f u ll b i as. 40 45 50 55 60 65 70 s i nad (db) input frequency (mhz) 0.1 1.0 10.0 00581-c-041 ?6.0dbfs ?0.5dbfs ? 20dbfs f i gure 41. sinad vs. input f r eque nc y (f cl o c k = 20 msp s ) ?100 ?9 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ?6 0 ?5 5 thd (db) input frequency (mhz) 0.1 1.0 10.0 00581-c-042 ? 6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 4 2 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 20 msp s ) 50 55 60 65 70 75 80 85 90 95 100 sd fr ( d b c ) input frequency (mhz) 0.1 1.0 10.0 00581-c-043 ?6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 4 3 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 2 0 ms ps) 40 45 50 55 60 65 70 s i nad (db) input frequency (mhz) 0.1 1.0 10.0 00581-c-044 ? 6.0dbfs ?0.5dbfs ?20dbfs f i gure 44. sinad vs. input f r eque nc y (f cl o c k = 10 msp s ) ?100 ?9 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ?6 0 ?5 5 thd (dbc ) input frequency (mhz) 0.1 1.0 10.0 00581-c-045 ? 6.0dbfs ?0.5dbfs ?20dbfs fi g u r e 4 5 . t h d v s . i n p u t fr e q u e n c y ( f cl ock = 10 msp s ) 50 55 60 65 70 75 80 85 90 95 100 sd fr ( d b c ) input frequency (mhz) 0.1 1.0 10.0 00581-c-046 ?6.0dbfs ?0.5dbfs ? 20dbfs fi g u r e 4 6 . s f d r v s . i n p u t fr e q u e n c y ( f cl o c k = 1 0 ms ps)
ad9260 rev. c | page 20 of 44 typical ac character i zation cu rves a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , a in = C0. 5 dbfs, dif f er en t i al d c c o u p l e d i n p u t w i t h c m l = 2 v . 50 55 60 65 70 75 80 85 90 95 100 s f dr (dbfs ) clock frequency (mhz) 5 01 0 1 5 00581-c-047 2 0 quarter bias half bias full bias f i g u re 47. sfdr v s . clo c k ra te (f in = 1 0 0 kh z in 8x m o de) 00581-c-048 full bias clock frequency (mhz) s f dr (dbfs ) 10 15 25 100 5 80 60 40 20 0 20 quarter bias half bias f i g u re 48. sfdr v s . clo c k ra te (f in = 5 0 0 kh z in 4x m o de) 00581-c-049 full bias clock frequency (mhz) s f dr (dbfs ) 10 15 25 100 5 80 60 40 20 0 20 quarter bias half bias f i g u re 49. sfdr v s . clo c k ra te (f in = 1.0 mhz i n 2 x m o de ) ?100 ?95 ?90 ?85 ?80 ?75 thd (dbc ) ?70 ?65 ?60 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 common mode input level (v) 00581-c-050 f in = 100khz, 8 mode f in = 1mhz, 2 mode f i gure 5 0 . thd vs . c o mmo n-mo d e in put l e v e l ( c ml) ?90 ?80 ?70 ?60 ?50 ?40 cmr (db) 1k 10k 100k 1m 10m 100m input frequency (hz) 00581-c-051 f s = 5mhz f s = 10mhz f s = 20mhz fi g u r e 5 1 . c m r v s . i n p u t fr e q u e n c y ( v cm l = 2 v p - p , 1x m o de) 75 80 85 90 95 100 s f dr (dbfs ) 0. 8 0. 6 0. 2 0 . 4 01 . 0 1 . 2 1 . frequency (mhz) 00581-c-052 4 1 . 6 4v span snr-8 mode 1.6v span snr-8 mode 4v span sfdr-2 mode 1.6v span sfdr-2 mode f i g u re 52. 4 v v s . 1. 6 v sp an s n r / sfdr (f cl o c k = 2 0 ms ps)
ad9260 rev. c | page 21 of 44 additiona l ac chara c terization curves a v d d = d v dd = d r vd d = +5 v , 4 v i n p u t s p a n , a in = C0. 5 db fs, dif f er en t i al d c c o u p l e d i n p u t wi t h c m l = 2 v , f u l l b i as, unles s ot he r w i s e note d . 80 85 90 95 100 105 s f dr (dbfs ) 110 115 120 ?5 0 ? 4 5 ?4 0 ? 3 5 ?3 0 ? 2 5 ?2 0 ? 1 5 ?1 0 ? 5 0 a in (dbfs) 00581-c-053 20 msps full bias 20 msps half bias 10 msps full bias 10 msps half bias f i gur e 5 3 . si ng le- t o n e sfdr vs . a m plitude (f in = 10 0 k h z, 8x m o d e ) 80 85 90 95 100 105 110 s f dr (dbfs ) ?5 0 ? 4 5 ?4 0 ? 3 5 ?3 0 ? 2 5 ?2 0 ? 1 5 ?1 0 ? 5 0 a in (dbfs) 00581-c-054 20 msps full bias 10 msps full bias 10 msps half bias f i gur e 5 4 . si ng le- t o n e sfdr vs . a m plitude (f in = 1.0 mh z) 80 85 90 95 100 105 110 s f dr (dbfs ) ?5 0 ? 4 5 ?4 0 ? 3 5 ?3 0 ? 2 5 ?2 0 ? 1 5 ?1 0 ? 5 0 a in (dbfs) 00581-c-055 20 msps full bias 10 msps full bias 10 msps half bias f i gur e 5 5 . si ng le- t o n e sfdr vs . a m plitude (f in = 50 0 k h z, 2x m o d e ) 50 60 70 80 90 100 110 120 w o rs t s p ur (dbc and dbfs ) ?40 ? 30 ? 6 0 ? 50 ?20 ? 10 0 a in (dbfs) 00581-c-056 20 msps (dbc) full bias 20 msps (dbfs) full bias 10 msps (dbfs) half bias 10 msps (dbc) half bias f i g u re 56. t w o - t o n e sfdr (f 1 = 4 7 5 k h z, f 2 = 52 5 m h z, 8 x mode) 50 60 70 80 90 100 110 120 w o rs t s p ur (dbc and dbfs ) ?40 ? 30 ? 6 0 ? 50 ?20 ? 10 0 a in (dbfs) 00581-c-057 full bias (dbc) full bias (dbfs) half bias (dbfs) half bias (dbc) f i g u re 57. t w o - t o n e sfdr (f 1 = 0.95 k h z , f 2 = 1. 05 m h z, 8x m o d e , 2 0 m s ps) 50 60 70 80 90 100 110 120 w o rs t s p ur (dbc and dbfs ) ?40 ? 30 ? 6 0 ? 50 ?20 ? 10 0 a in (dbfs) 00581-c-058 dbc dbfs f i g u re 58. t w o - t o n e sfdr (f 1 = 1 . 9 m h z, f 2 = 2. 1 m h z, 4 x m o de 20 m s p s )
ad9260 rev. c | page 22 of 44 lsb differentiator v in int1 + ? 5b dac1 + ? 5b dac2 5b adc int2 5b dac + ? 16 3b adc 3b dac + ? 4 3b adc 3b dac + ? 4 4b adc pipeline correction logic 8 lsbs ++ c out half-band decimation filter stage 1 half-band decimation filter stage 2 half-band decimation filter stage 3 z ?d shuffle m out control/test logic bandgap reference reference buffer output bits 00581-c-059 f i g u re 59. si mpl i f i e d bl ock d i ag r a m
ad9260 rev. c | page 23 of 44 theory of operation the ad9260 utilizes a new analog-to-digital converter architecture to combine sigma-delta techniques with a high speed, pipelined a/d converter. this topology allows the ad9260 to offer the high dynamic range associated with sigma- delta converters while maintaining very wide input signal bandwidth (1.25 mhz) at a very modest 8 oversampling ratio. figure 59 provides a block diagram of the ad9260. the differential analog input is fed into a second order, multibit sigma-delta modulator. this modulator features a 5-bit flash quantizer and 5-bit feedback. in addition, a 12-bit pipelined a/d quantizes the input to the 5-bit flash to greater accuracy. a special digital modulation loop combines the output of the 12- bit pipelined a/d with the delayed output of the 5-bit flash to produce the equivalent response of a second order loop with a 12-bit quantizer and 12-bit feedback. the combination of a second order loop and multibit feedback provides inherent stability: the ad9260 is not prone to the idle tones or full-scale idiosyncrasies sometimes associated with higher order single bit sigma-delta modulators. the output of this 12-bit modulator is fed into the digital decimation filter. the voltage level on the mode pin establishes the configuration for the digital filter. the user may bring the data out undecimated (at the clock rate), or at a decimation factor of 2, 4, or a full 8. the spectra for these four cases are shown in figure 11, figure 12, figure 13, and figure 14, all for a 100 khz full-scale input and 20 mhz clock. the spectra of the undecimated output clearly shows the second order shaping characteristic of the quantization noise as it rises at frequencies above 1.25 mhz. the on-chip decimation filter provides excellent stopband rejection to suppress any stray input signal between 1.25 mhz and 18.75 mhz, substantially easing the requirements on any antialiasing filter for the analog input path. the decimation filters are integrated with symmetric fir filter structures, providing a linear phase response and excellent passband flatness. the digital output driver register of the ad9260 features both read and chip select pins to allow easy interfacing. the digital supply of the ad9260 is designed to operate over a 2.7 v to 5.25 v supply range, though 3 v supplies are recommended to minimize digital noise on the board. a data available pin allows the user to easily synchronize to the converters decimated output data rate. out-of-range (otr) indication is given for an overflow in the pipelined a/d converter or digital filters. a resetb function is provided to synchronize the converters decimated data and clear any overflow condition in the analog integrators. an on-chip reference and reference buffer are included on the ad9260. the reference can be configured in either a 2.5 v mode (providing a 4 v p-p differential input full scale), a 1 v mode (providing a 1.6 v p-p differential input full scale), or programmed with an external resistor divider to provide any voltage level between 1 v and 2.5 v. however, optimum noise and distortion performance for the ad9260 can only be achieved with a 2.5 v reference, as shown in figure 52. for users who want to operate the part at reduced clock frequencies, the bias current of the ad9260 is designed to be scalable. this scaling is accomplished through use of the proper external resistor tied to the bias pin: the power can be reduced roughly proportionately to clock frequency by as much as 75% (for clock rates of 5 mhz). refer to figure 47 to figure 49 and figure 53 to figure 57 for characterization curves showing performance tradeoffs.
ad9260 rev. c | page 24 of 44 analog input and r eference overview f i gur e 60, a sim p lif i ed m o de l o f th e ad9260, hig h lig h ts t h e r e l a ti o n s h i p b e t w e e n th e a n a l o g i n p u t s , v i n a , v i n b a n d th e r e fer e n c e v o l t a g e vref . l i k e t h e v o l t a g e a p plie d t o t h e t o p o f t h e r e sis t o r l a dder in a f l as h a/ d co n v er t e r , t h e val u e vref def i n e s t h e max i m u m i n p u t v o l t a g e t o t h e a/ d co n v er t e r . an in t e r n al r e f e r e nce b u f f er in t h e ad9260 s c ales t h e r e f e r e n c e v o l t a g e vref b e f o r e i t is a p p l ie d in t e r n al l y t o t h e ad9260 a/d co r e . the s c ale f a c t o r o f t h is r e f e r e n c e b u f f er is 0.8. c o n s e q uen t ly , t h e maxim u m in p u t v o l t a g e t o t h e a/d co r e is +0.8 vref . th e minim u m i n p u t v o l t a g e t o t h e a/d co r e is a u to m a t i c a l l y def i n e d to b e C0. 8 vref . w i t h t h is s c a l e fac t o r , t h e maxi m u m dif f er en t i al in pu t s p a n o f 4 v p-p is ob t a i n e d wi t h a vref v o l t a g e o f 2.5 v . a smal ler dif f er en t i al i n p u t s p a n ma y b e ob tain e d b y usin g a vref v o l t a g e o f les s tha n 2.5 v a t t h e exp e n s e o f ac p e r f o r ma n c e (r efer t o f i gur e 52). a/d core ? 0.8 vref +0.8 vref 16 + ? vina vinb 00581-c-060 f i g u re 60. si mpl i f i e d input m o d e l inpu t span the ad9260 is im p l em en t e d wi th a dif f er en t i al in p u t s t r u c t ur e . this s t r u c t ur e a l lo ws t h e co mmo n - m o d e le ve l ( a v e ra g e v o l t a g e o f th e t w o in p u t p i n s ) o f th e in p u t si gn al t o be va ri ed inde p e n d e n t l y o f t h e i n p u t s p an o f t h e co n v er t e r o v er a w i de ra n g e , as sh o w n in f i gur e 50. s p e c if ica l ly , t h e i n p u t t o t h e a/ d co r e is t h e dif f er en c e o f t h e v o l t a g es a p pli e d a t t h e vi n a and v i n b i n pu t pi n s . t h e r e f ore, t h e e q u a t i on , vinb vina vcore ? = ( 1 ) def i n e s t h e o u t p u t o f t h e dif f er en t i al i n p u t s t a g e a nd p r o v ides t h e in p u t t o t h e a/d co r e . the vol t ag e, vc or e , m u s t s a ti sf y th e co n d i t i o n, vref vcore vref + ? 8 . 0 8 . 0 ( 2 ) w h er e vref is t h e v o l t a g e a t t h e vref p i n. inpu t com p liance range i n addi t i on t o t h e l i mi t a t i o n s on t h e dif f er en t i a l s p a n o f t h e i n p u t si gn al in di ca t e d i n eq ua t i o n 2, a n ad di ti o n al li mi t a ti o n i s place d on t h e in p u ts b y t h e a n al og in p u t s t r u c t u r e o f t h e ad9260. the analog in p u t s t r u c t ur e bo u n ds t h e valid o p era t ing r a n g e fo r vin a a nd vin b . t h e co n d i t ion, v avdd vinb v avss v avdd vina v avss 5 . 0 5 . 0 5 . 0 5 . 0 + < < + ? < < + (3) w h er e av s s is no mina l l y 0 v and av d d is n o minal l y +5 v , def i n e s t h is r e quir em e n t. t h us t h e va li d i n p u ts fo r vin a a nd vinb a r e an y c o m b in a t io n t h a t s a t i sf ies b o t h e q ua t i o n s 2 and 3. n o t e t h a t t h e cl o c k clam p i n g met h o d us e d i n t h e dif f er en t i al dr i v er cir c ui t sho w n i n f i gur e 6 3 is s u f f i cien t fo r p r o t e c t i n g t h e ad9260 in a n u n der v ol ta g e condi tion. f o r addi t i o n a l i n fo r m a t io n sh o w i n g t h e r e la t i on sh i p s b e twe e n vin a , vinb , vref , a n d t h e dig i tal o u t p u t o f th e ad9260, s e e t a b l e 13. refer to t a bl e 1 2 fo r a su mmar y o f t h e var i o u s ana l o g in p u t and re f e re nc e c o n f i g u r a t i o ns . analog input opera t ion the a n alog in p u t s t r u c t ur e o f t h e ad9260 is op timize d t o m e et t h e p e r f o r ma n c e r e q u ir e m en ts fo r s o m e o f t h e m o s t demanding co mm un ic a t io n a nd da t a acq u is i t io n a p pli c a t ion s . this in pu t st r u c t u r e i s c o m p o s e d of a s w itc h e d - c a p a c itor n e t w or k t h at s a m p les t h e i n pu t sig n a l a p plie d to p i n s vin a a nd vi nb o n e v er y r i sin g e d g e o f t h e clk pi n. th e in p u t s w i t ch e d ca p a c i t o rs are ch arge d to t h e i n put volt age d u r i ng e a ch p e r i o d of c l k . t h e r e su l t in g cha r ge, q, o n t h e s e c a p a ci t o rs is e q ua l to c v in , w h er e c is t h e i n p u t ca p a c i t o r . the cha n g e in cha r g e o n t h e s e ca p a ci t o rs, de l t a q , as th e ca p a ci t o rs a r e c h a r g e d f r o m a p r evio u s s a m p le o f t h e in p u t sig n al t o t h e n e xt s a m p le , is a p p r o x ima t e d in t h e fol l o w in g e q ua t i o n , ( ) 2 ~ ? ? = n n n v v c deltav c q delta (4) w h er e v n r e p r es en ts t h e p r e s en t s a m p le o f t h e i n p u t sig n al an d v nC2 r e p r es en ts t h e s a m p le t a k e n tw o clo c k c y cles e a rlier . th e a v era g e c u r r e n t f l o w in t o t h e in p u t (p r o vi de d f r o m a n ext e r n al s o ur ce) is g i v e n in t h e fol l o w in g e q ua t i o n , ( ) clock n n f v v c t q delta i ? = ? 2 ~ / (5) w h er e t r e p r es e n ts t h e p e r i o d o f clk an d f cl o c k r e p r es en ts t h e f r e q u e nc y of c l k . e q u a t i ons 4 an d 5 pro v i d e s i m p l i f y i n g a p p r o x ima t io n s o f t h e o p er a t ion o f t h e a n alog in p u t s t r u c t ur e o f th e ad9260. a m o r e exac t, det a iled des c r i p t ion an d a n al ysis o f t h e in p u t o p era t io n fol l o w s.
ad9260 rev. c | page 25 of 44 analog modulator vina vinb ss1 ss2 cs1 cs2 ss3 sh1 ss4 sh2 sh3 sh4 cpb1 cpb2 cpa1 cpa2 00581-c-061 f i g u re 61. d e t a iled a n al og input st ru c t ur e f i gur e 61 il l u s t ra t e s t h e a n alog in p u t s t r u c t ur e o f th e ad9260. f o r t h e m o m e n t , ig n o r e t h e p r e s ence o f t h e p a rasi t i c c a p a ci t o rs cp a a nd c p b . the ef fe c t s o f t h es e p a rasi t i c c a p a ci t o rs wi l l b e dis c uss e d n e a r t h e e nd o f t h is s e c t io n. t h e sw i t ch e d ca p a c i to rs, cs1 a nd cs2, s a m p le t h e in p u t v o l t a g es a p pl ie d o n p i n s vin a a nd vi nb . t h e s e c a p a ci to rs a r e co nne c t e d to i n p u t pin s vi n a a nd vi nb w h en cl k is lo w . w h en clk r i s e s, a s a m p le o f t h e in p u t sig n al is t a k e n on ca p a c i to rs cs1 a nd cs 2. w h e n clk is hig h , ca p a c i t o rs cs1 a nd cs2 a r e co nnec t e d t o t h e analog m o d u l a tor . t h e mo d u l a tor pre c h a rge s c a p a c i tor s c s 1 and c s 2 to m i n i m i z e t h e amou n t of ch ar ge re qu i r e d f r om a n y c i rc u i t us ed in com b ina t io n wi th t h e ad9260 t o dr i v e in p u t p i n s vi n a a nd vi nb . this r e d u ces t h e i n pu t dr i v e r e q u ir e m e n ts o f t h e a n a l o g cir c ui t r y dr i v in g pin s vi n a and vin b . the ana l o g m o d u l a t o r p r e c ha rg es t h e v o l t ag es acr o s s ca p a ci t o rs cs1 an d cs2, a p p r o x im a t e l y e q u a l t o a d e l a ye d v e rsio n of t h e in pu t sig n al . w h en ca p a ci t o rs cs1 and cs2 a r e co nnec t e d t o in p u t p i n s vi n a and vinb , t h e dif f er en t i al cha r g e , q(n), o n t h es e ca p a ci t o rs is g i ven in t h e f o l l o w in g eq ua t i o n , vcore cs q q n q = ? = 2 1 ) ( ( 6 ) w h er e q 1 and q 2 are t h e i n d i v i d u a l ch arge s store d on c a p a c i tors cs1 a nd cs2 r e sp e c t i vely , and cs is t h e c a p a ci t a n c e val u e o f cs1 a nd cs2. w h en ca p a c i t o rs cs1 a nd cs2 ar e co nn ec t e d t o t h e a n a l o g m o du l a t o r du r i n g t h e pr e c e d i n g pr e c h a r g e c l o c k p h a s e , t h e ca pa ci t o r s a r e p r ec h a r g ed eq ual t o a n a p p r o x i m a t i o n o f a p r evio us s a m p le o f the in p u t sig n al . c o n s e q uen t l y t h e dif f er en t i al cha r g e o n t h es e ca p a ci t o rs w h i l e c l k is hi g h is gi v e n i n th e f o ll o w i n g e q u a ti o n , () vdelta cs delay vcore cs n q + = ? ) 1 ( (7) w h er e vc or e ( d e l a y ) is t h e val u e o f v c o r e s a m p le d d u r i n g a p r evio us p e r i o d o f clk, an d vd e l t a is t h e sig m a-del t a er r o r vol t age l e f t on t h e c a p a c i tors . v d el t a i s a n a t u r a l ar t i f a c t of t h e sig m a- delt a fe e d b a ck t e chniq u es u t i l i z e d in t h e ana l og m o d u l a t o r o f the ad9260. i t is a smal l ra ndo m v o l t a g e t e r m t h a t chan ges e v er y clo c k p e r i o d an d v a r i es f r o m 0 t o 0.05 vref . the a n alog cir c ui t r y us e d t o dr i v e t h e i n p u t p i n s o f t h e ad92 60 m u s t r e s p ond to th e c h a r g e g l i t c h tha t o c c u rs when ca p a c i t o rs cs1 a nd cs2 a r e co nne c t e d to i n p u t pin s vi n a a nd vin b . t h i s c i r c u i t r y m u s t p r o v i d e a d d i ti o n a l c h a r g e , qd e l ta , t o c a pa c i t o r s cs1 a nd cs2, w h ich is t h e dif f er en ce b e tw e e n t h e p r e c ha rg e d va l u e, q(n C 1), and t h e n e w va l u e, q(n), as g i ve n i n t h e fol l o w ing e q u a t i o n , ( ) ( ) 1 ? ? = n q n q qdelta ( 8 ) () [ ] vdelta delay vcore vcore cs qdelta + ? = (9) drivi n g th e inpu t tra n sient res p onse the c h a r g e g l i t ch o c c u rs on ce a t the b e g i nnin g o f ev er y p e r i o d o f t h e i n p u t cl k (fa l ling e d ge), a nd t h e s a m p le is t a k e n on ca p a ci t o rs cs1 a nd cs2 exac tl y o n e-half p e r i o d la t e r (r isin g e d g e ) . fi g u re 6 2 pre s e n t s a t y pi c a l i n put w a ve f o r m a p p l i e d to in p u t p i n s vi n a a nd vi nb o f th e ad9260. clock vina-vinb track sample track sample track sample track sample 00581-c-062 f i gure 62. t y pic a l i n put w a v e form f i gur e 62 il l u s t ra t e s t h e ef fe c t o f t h e cha r g e g l i t ch w h e n a s o ur ce wi t h n o nzer o o u t p ut im p e dan c e is us e d t o dr i v e t h e i n p u t pin s . this s o ur ce m u s t b e c a p a b l e o f s e t t ling f r o m the c h a r g e g l i t ch in o n e- half p e r i o d o f t h e cl k. u n fo r t una t e l y , t h e mos swi t ch es us e d i n an y cmos-s wi tch e d c a p a ci to r cir c ui t (i n c l u ding t h o s e in t h e ad9260) in cl ude n o nl in e a r p a rasi tic j u n c tio n ca p a ci tan c es conn ec t e d t o t h eir t e r m inals. f i gu r e 61 als o il l u s t ra t e s t h e p a rasi t i c ca p a c i t a n c es, c p a1, c p b1, c p a2, a nd c p b 2 , a s s o ci a t ed w i th th e i n p u t s w i t c h e s . p a rasi tic ca p a ci to r c p a1 a n d c p a2 a r e al wa ys co nn ec t e d t o p i n s vin a and vi n b a nd t h er efo r e do n o t con t r i b u te to t h e g l i t ch en erg y . p a rasi tic ca p a ci t o rs c p b1 a nd c p b2 , o n t h e o t h e r hand , ca us e a c h a r g e g l i t c h tha t adds to tha t o f in p u t c a p a ci t o rs cs1 a nd cs2 w h e n t h e y a r e co n n e c te d to i n p u t pi n s vin a and v i n b . t h e non l i n e a r j u nc t i on c a p a c i t a nc e of cpb 1 a n d cp b 2 ca us e c h a r g e g l i t c h en erg y tha t is n o nl in ea r i l y r e l a t e d t o t h e in p u t sig n al . ther efo r e , lin e a r s e t t l i n g is dif f i c u l t t o achi e v e unles s t h e in p u t s o ur ce co m p lete l y s e t t les d u r i ng o n e-half p e r i o d o f cl k. a p o r t io n o f t h e g l i t ch i m p u ls e en erg y kick e d bac k a t t h e s o urce is n o t lin e a r ly r e la t e d t o t h e in p u t sig n al . ther efo r e , t h e b e s t w a y t o en s u re t h a t t h e i n p u t sig n al s e t t les line a r ly is to us e wi de b a nd w i d t h cir c ui t r y , w h i c h s e t t les as co m p lete l y as p o s s i b le f r o m t h e g l i t ch d u r i n g on e - half p e r i o d of th e c l k . the ad9260 u t ilizes a p r o p r i et a r y c l o c k-bo os ted b o o t - s t ra p p i n g t e c h niq u e t o r e d u ce t h e n o nlin ea r p a rasi tic
ad9260 rev. c | page 26 of 44 ca p a ci tan c es o f th e in t e r n al cmos swi t ch es. this t e c h niq u e im p r o v es t h e li ne a r i t y o f t h e i n pu t sw i t ch es and r e d u ces t h e n o nlin ea r pa ra si ti c ca pa ci ta n c e . t h us, th i s t e c h n i q u e r e d u ce s t h e n o nli n e a r g l i t ch energ y . th e ca p a ci t a n c e v a l u es fo r t h e in p u t ca p a ci t o rs a nd p a rasi tic ca p a c i to rs f o r th e in p u t s t r u c t ur e o f the ad9260, as il l u s t ra t e d in f i gure 61, a r e lis t e d as f o l l o w s. cs = 3.2 pf , c p a = 6 pf , c p b = 1 pf (wh e r e cs is th e ca p a ci tan c e val u e o f ca p a ci t o rs cs1 a nd cs2, c p a is the val u e o f ca p a ci t o rs c p a1 a nd c p a2, an d c p b is t h e va l u e o f ca p a ci t o rs c p b1 a nd c p b2 ). the to t a l ca p a ci t a n c e a t e a ch i n p u t pin is c in = cs + c p a + c p b = 10.2 pf . input driver c o nsiderations t h e o p t i m u m n o i s e a n d di st or t i on p e r f or m a n c e of t h e a d 9 2 6 0 c a n onl y be a c h i e v ed when the ad9 2 6 0 i s d r i v en d i f f er en ti a l l y wi t h a 4 v i n p u t s p a n . si nc e not a l l a p pl i c a t i o ns h a ve a s i g n a l p r e c o n di t i on e d fo r dif f er en t i al o p era t ion, t h er e is o f t e n a n e e d t o p e r f o r m a sing le-e n d e d - t o-di f f er en t i al con v e r sio n . i n t h e cas e o f t h e ad9 260, a sin g le-ende d-t o -dif f e r e n t ial con v ersion is bes t r e aliz e d usi n g a di f f er en tial o p a m p d r i v er . a l t h o u g h a tra n sfo r m e r wil l p e r f o r m a simi la r f u n c t i o n fo r ac sig n als, i t s us ef u l n e ss is p r e c l u de d b y i t s i n a b i l i t y to dir e c t ly dr i v e t h e ad9260 an d th us th e addi tio n a l r e q u ir emen t o f a n ac ti ve lo w nois e , l o w distor t i on b u f f e r st ag e. single-ende d - t o-diffe renti a l op a m p dri v er ther e a r e tw o si n g le-e nde d-t o - d if fer e n t i a l o p am p dr i v er cir c ui ts us ef u l f o r dr i v in g t h e ad9260. th e f i rst cir c ui t, sh o w n in f i gur e 63, us es th e ad8138 a nd r e p r es en ts t h e best c h oice in m o st a p plic a t ion s . t h e ad813 8 is a lo w di st o r t i o n d i f f er en t i a l ad c dr i ver desig n e d to con v er t a g r o u nd-r e fer e n c e d sing le- en d e d i n p u t si g n al t o a di f f er en ti al o u t p u t si gnal wi t h a sp e c if ie d co m m o n - m o d e le ve l fo r dc-co u plin g a p plic a t io n s . i t i s ca p a b l e o f main t a ini n g t h e typ i cal thd and s f d r p e r f o r ma n c e o f th e ad9260 wi th o n l y a s l ig h t deg r ada t ion in i t s n o is e p e r f o r ma n c e in th e 8 m o de (i . e . , s n r o f 85 db C86 db). i n this a p p l ica t io n, t h e ad8138 is co nf igur ed f o r uni t y ga in an d i t s co mm on-m o d e o u t p u t l e v e l is s e t t o 2.5 v , f u n c tionin g l i k e th e vref o f the ad9260, t o maximize i t s o u t p u t h e adr o om wh ile o p e r a t in g f r o m a si n g le s u p p l y . n o t e th a t t h e sin g le - su p p ly o p era t ion has t h e b e n e f i t o f n o t r e q u ir ing a n i n p u t p r o t ec tio n n e two r k f o r th e ad9 260 in dc -co u p l ed a p p l ica t io n s . a s i m p l e r - c n e t w or k a t t h e output i s u s e d to f i lte r out h i g h f r eq uen c y n o is e f r o m th e ad81 38. rec a l l , t h e ad9260 s smal l sig n al b a n d wi d t h is 75 mh z. th er efo r e , a n y n o is e fal l i n g wi t h i n th e bas e band ban d wid t h o f t h e ad9260 def i n e d b y i t s s a m p le a nd de ci ma t i o n r a te, as wel l as i m a g es o f i t s b a s e b a nd r e sp o n s e o c c u r r i n g a t m u l t i p les o f the s a m p le ra te , wil l deg r ade i t s o v era l l noi s e p e r f or m a nc e . vin 499 ? 50 ? +5v ad9260 vina vref c s 100pf 0.1 f 10 f vinb c s 100pf 499 ? 499 ? 499 ? 50 ? ad8138 00581-c-063 f i gure 63. ad8138 single -ended d i fferential adc d r ive r the s e cond dr i v er cir c ui t, sho w n i n f i gur e 64, c a n p r o v ide s l ig h t l y enhan c e d n o is e p e r f o r ma n c e re l a ti v e t o th e ad8138, as s u min g lo w no is e , hig h sp eed o p a m ps a r e us ed . this dif f er en t i a l o p am p dr i v er cir c u i t is co nf igur e d to co n v er t a nd l e vel - s h i f t a 2 v p - p s i ng l e - e nd e d , g r ou n d - re fe re nc e d s i g n a l to a 4 v p-p dif f er en t i al sig n al ce n t e r e d a t t h e co mm o n - m o d e le vel o f th e ad9260. the cir c ui t is bas e d o n tw o o p am ps tha t a r e co nf igur e d as m a t c h e d u n i t y ga i n d i f f er en ce a m plif iers. t h e sin g le-e nde d in p u t sig n a l is a p plie d t o o p p o sin g in p u ts o f t h e dif f er en ce am pl if iers, t h us p r o v idi n g dif f er en t i a l o u t p uts. th e co mm on- m o d e o f fs et vol t a g e is a p plie d to t h e no ni n v er t i n g r e sist o r leg o f e a ch d i f f er en ce am plif ier p r o v id i n g t h e r e q u ir e d of f s e t vol t age. t h i s of f s e t vol t ag e i s de r i ve d f r o m t h e c o m m on - m o de leve l (cm l ) p i n o f t h e ad9260 via a lo w o u t p u t im p e dan c e b u f f er a m plif ier ca p a b l e o f dr iving a 1 f ca p a ci t i ve lo ad . th e co mm o n - m o d e o f fs et can b e va r i e d o v er a 1.8 v t o 2 . 5 v sp an w i t h out an y s e r i ou s d e g r a d a t i o n i n d i stor t i on p e r f or m a nc e a s sh ow n i n fi g u re 5 0 , t h u s pro v i d i n g s o me f l e x ibi l it y i n i m pro v i n g output c o m p re ss i o n d i s t or t i on f r om s o me 5 o p a m ps wi th l i mi t e d p o si ti v e v o l t a g e swin g. t o p r o t ec t the ad9260 f r o m a n u n der v ol ta g e fa u l t con d i t ion f r om op am p s sp e c i f i e d f o r 5 v op e r a t i o n , t w o 5 0 ? s e r i e s r e sis t o r s a n d a dio d e t o a g nd a r e in s e r t e d b e tw e e n e a ch o p a m p o u t p u t and th e ad9260 in p u ts. the ad92 60 wil l i n he re n t ly b e prote c te d ag ai nst an y o v e r volt age c o nd i t i o n i f t h e op am p s share t h e s a me p o s i t i v e p o we r sup p ly ( a v d d ) as t h e ad9260. n o t e , th e gain acc u rac y a n d co mm o n -mo d e r e jec t io n o f e a ch d i f f er en ce a m plif ier i n t h is dr i v er cir c ui t ca n b e e n h a nc e d b y u s i n g a m a tc he d t h i n - f i l m re s i stor ne t w or k (o hm t e k o r n a 5000f) f o r th e o p a m ps. resisto r val u es sh o u ld be 500 ? o r les s t o ma in t a in t h e lo w e s t p o s s i b le n o is e. the n o is e p e r f o r ma n c e o f e a ch uni t y ga in dif f er en t i al dr i v er cir c ui t is li mi t e d b y i t s i n h e r e n t n o is e ga in o f t w o . f o r uni t y gain op am p s on ly , t h e noi s e g a i n c a n b e re d u c e d f r om t w o to o n e
ad9260 rev. c | page 27 of 44 v in c c 100pf c d 100p f v cml -vin 50 ? r 50 ? c f r r c f r r r r r 50 ? v cml -vin 0.1 f 1.0 f ad817 ad9260 50 ? vina vinb cml c c 100pf 00581- c - 064 f i g u re 64. dc- c ou pled d i f f e rent i a l d r iver w i t h l e ve l-shif t i ng bey o n d t h e in p u t si gn als pa s s b a n d b y ad di n g a s h un t ca pa ci t o r , c f , a c ro ss t h e f e e d b a c k re s i stor of e a ch op am p . t h i s w i l l es s e n t i a l l y es t a blis h a l o w-p a ss f i l t er w h ich r e d u ces t h e n o i s e ga in t o on e b e yo n d t h e f i l t er s f C3 db w h i l e s i m u l t ane o u sly b a n d l i m i ti n g th e i n p u t s i gn a l t o f C3 d b . n o t e th a t th e po le es ta b l is hed b y t h is f i l t er ca n als o be us ed as t h e r e al p o le o f a n an t i a l i a s i ng f i lte r . si nc e t h e noi s e c o n t r i b u t i on o f t w o op am p s f r o m t h e s a m e p r o d uc t fa mi ly a r e typ i ca l l y e q ua l b u t un co r r ela t e d , t h e t o t a l o u t p ut-refer r e d n o is e o f e a ch o p am p wi l l a dd r o o t -su m s q ua r e le a d i n g to a f u r t h e r 3 db d e g r ad a t ion in t h e c i r c ui t s no is e p e r f o r ma nce. f u r t h e r o u t- o f -b a nd n o is e r e d u c t io n ca n b e r e a l i z e d w i t h t h e a d d i t i on o f sin g le-e nde d and dif f er en t i a l c a p a ci to rs, c s a nd c d . t h e d i stor t i on a n d noi s e p e r f or m a nc e of t h e t w o op am p s w i th in t h e si gna l pa th a r e cri t ica l i n a c hi e v in g o p ti m u m p e r f o r ma n c e in th e ad9260. l o w n o is e o p a m p s ca p a b l e o f p r o v idin g g r e a ter tha n 85 db thd a t 1 m h z w h ile swin g i n g o v er a 1 v t o 3 v ra n g e a r e a rar e co mm o d i t y , yet t h es e p a r t s a r e th e onl y o n es tha t sh o u ld b e co n s ider ed . th e ad9632 o p a m p w a s f o u n d to pro v i d e sup e r b d i stor t i on p e r f or m a nc e i n t h i s c i rc u i t d u e to it s ab i l i t y to ma i n t a i n e x c e l l e n t di s t or t i on p e r f o r ma n c e o v er a wi de b a ndwi d t h w h i l e s w i n g i n g o v er a 1 v t o 3 v ra n g e . s i n c e the ad9632 is ga in-o f-tw o o r g r ea t e r s t a b le, t h e us e o f t h e no is e r e d u c t ion sh un t ca p a c i t o rs dis c us s e d ab o v e was p r ohi b i t e d , t h us deg r a d ing i t s n o is e p e r f o r ma n c e sl ig h t ly (1 dbC2 db) w h en co m p a r ed t o th e o p a642. n o t e tha t t h e ma jo r i ty o f the ad9260 t e st and c h a r ac t e r i za t i o n da t a p r es en ted in this da t a sh eet was taken using th e ad9632 op a m p in this dc-co u ple d dr i v er cir c ui t. this dr i v er cir c ui t is a l s o p r o v ide d on th e ad9260 eva l ua t i o n bo a r d sin c e the ad8138 was unr e leas ed at t h at t i m e . t h e output s of e a ch op a m p are a c c o upl e d v i a a s m a l l s e r i e s r e sis t o r a n d ca p a ci t o r (i .e ., 50 ? a nd 0.1 f) t o t h e r e s p ec ti v e in p u ts o f t h e ad9260. s i mi la r t o th e dc co u p le d dr i v er , f u r t her o u t-o f -b and n o is e r e d u c t ion can b e r e a l i z e d wi t h t h e a d d i t i on o f 100 pf sin g le-en d e d and dif f er en t i al c a p a ci t o rs, c s and c d . the l o w e r c u t o ff fr e q u e n c y o f t h i s a c - c o u p l e d c i r c u i t i s d e t e r m i n ed by r c an d c c in wh i c h r c is tie d t o th e comm o n -mo d e l e v e l p i n, cml, o f the ad9260 f o r p r o p er b i asin g o f t h e in p u ts. al t h o u g h th e o p a642 was f o un d t o p r o v ide t h e lo w e s t o v eral l n o is e and dis t o r tio n p e r f o r ma n c e (88.8 db a nd 96 db th d @ 100 kh z), th e ad8055, o r d u al ad8056, suf f er ed o n l y a 0.5 db t o 1.5 db d e grad a t i o n in o v erall perf o r m a n c e . i t i s w o r t h n o tin g tha t g i v e n t h e hig h l e v e l o f p e r f o r ma n c e a t ta ina b le b y t h e ad9260, s p eci a l co n s id e r a t i o n m u s t be gi v e n t o bo th th e q u ali t y o f th e t e s t eq ui p m en t a n d t e s t se t- u p in i t s eval ua ti o n . common-mo de le vel t h e c m l pi n i s an i n te r n a l an a l o g b i a s p o i n t u s e d i n te r n a l ly b y th e ad9260. this p i n m u s t be deco u p led t o a n a l og g r o u n d wi t h a t leas t a 0.1 f ca p a ci t o r as sh o w n in f i gur e 65 . the dc le v e l o f cml is a p p r o x i m a t e l y a v dd/2 .5. this v o l t a g e sh o u l d b e b u f f er ed if i t is to be us ed f o r a n y ext e r n al b i asin g. n o t e : t h e co mmo n - m o d e v o l t a g e o f t h e in pu t sig n al a p plie d t o th e ad9260 n e ed n o t be a t t h e exac t s a m e leve l as cml. w h ile t h is le vel is r e co mmende d fo r o p t i ma l p e r f o r ma n c e, t h e ad9260 is t o lera n t o f a ra n g e o f in p u t co mm o n -mo d e v o l t a g es a r o u n d a v d d /2.5. cml ad9260 0.1 f 00581-c-065 f i g u re 65. c m l d e coupl i ng
ad9260 rev. c | page 28 of 44 reference operation the ad9260 con t a i n s a n on-bo a r d ban d ga p r e f e r e n c e an d i n te r n a l re f e re n c e bu f f e r am p l i f i e r . t h e o n b o ard re f e re nc e prov i d e s a pi n - s t r a pp abl e opt i on to g e n e r a te e i t h e r a 1 v or 2 . 5 v o u t p u t . w i t h t h e addi t i on o f t w o ext e r n al r e sis t o r s, t h e us er ca n g e n e ra t e r e f e r e n c e v o l t a g es o t h e r than 1 v a nd 2.5 v . an o t h e r al t e r n a t i v e is t o us e an ext e r n al r e fer e nce fo r desig n s r e q u ir in g e n hance d acc u r a c y a nd/o r dr if t p e r f o r ma n c e. s e e t a b l e 12 f o r a s u mma r y o f th e p i n - s t ra p p in g o p tio n s f o r th e ad9260 r e f e r e nce co nf igura t ion s . n o te , t h e optim u m n o i s e a n d d i s t o r tio n ca n o n l y be ac h i e v ed w i th a 2. 5 v r e fe r e nc e. fi g u r e 6 6 s h ow s a s i m p l i f i e d m o d e l o f t h e i n t e r n a l v o lt a g e r e f e r e n c e o f the ad9260. a p i n-s t ra p p a b le r e f e r e n c e a m p l if ier bu f f e r s a 1 v f i x e d re f e re nc e. t h e output f r om t h e re f e re nc e a m plif ier , a1, a p p e a r s o n t h e v r ef p i n and m u st b e de co u p le d wi th 0.1 f and 10 f ca p a ci t o r t o refco m . th e v o l t a g e o n t h e vref p i n det e r m i n es t h e f u l l -s cale in p u t sp a n o f t h e a/d . this i n p u t sp a n e q ua ls: vref span input scale full = 6 . 1 - the v o l t a g e a p p e a r in g a t t h e v r ef p i n, as we l l as t h e s t a t e o f t h e in t e r n a l r e fer e n c e am plif ier , a1, is deter m i n e d b y t h e v o l t a g e a p p e a r i n g a t t h e s e nse p i n. the log i c cir c ui t r y co n t a i n s t w o c o m p ar a t ors t h a t mon i tor t h e volt age a t t h e se n s e pi n . the co m p a r a t o r wi t h t h e lo w e st s e t p o i n t ( a p p r o x ima t e l y 0.3 v ) co n t r o ls th e posi ti o n o f t h e swi t c h wi thi n t h e f eed ba ck pa t h o f a1. i f t h e s e ns e p i n is t i e d t o refc o m , t h e s w i t c h is c o nne c te d to t h e i n te r n a l re s i st or ne t w ork , t h u s pro v i d i n g a vref o f 2.5 v . i f th e s e ns e p i n is tied t o t h e v r ef p i n via a shor t or re s i stor , t h e s w itc h i s c o n n e c te d to t h e se n s e pi n . a s h o r t wi l l p r o v i d e a v r ef o f 1.0 v w h i l e an exter n al r e sis t o r n e tw o r k wi l l p r o v i d e an a l t e r n a t i v e vref s p a n b e t w e e n 1 . 0 v a nd 2.5 v . th e ext e r n al r e sis t o r n e tw o r k, f o r exa m p l e , ma y be im ple m e n te d as a r e sisto r divid e r cir c ui t. this divid e r cir c ui t co u l d co n s ist o f a r e sisto r (r1) co nn e c te d b e twe e n vref and s e ns e an d an ot h e r r e sisto r (r 2) co nn e c te d b e tw e e n s e n s e an d r e f c om . t h e ot he r c o m p ar a t or c o n t ro l s i n te r n a l c i rc u i t r y t h a t wi l l dis a b l e t h e r e fer e nce am plif ier if t h e sens e p i n is t i e d t o a v dd . dis a b l in g t h e r e fer e n c e am plif ier a l l o ws t h e v r ef p i n to b e dr i v e n b y a n ex ter n a l vol t a g e r e fer e n c e. logic logic ? + ad9260 1v disable a1 to a/ d 5k ? 5k ? a2 6.25k ? 6.25k ? disable a2 a1 7.5k7.5k ? 5k ? capt capb vref sense refcom 00581-c-066 f i gure 6 6 . sim p li fied refer e nc e t h e re f e re nc e bu f f e r c i rc u i t l e vel sh i f t s t h e re f e re nc e to a n a p p r o p r i a t e comm on- m o d e vol t a g e fo r us e b y t h e i n t e r n al cir c ui t r y . th e on-chi p b u f f er p r o v ides t h e lo w i m p e dan c e n e cess a r y fo r dr i v in g t h e in t e r n a l sw i t ch e d c a p a ci t o r cir c ui ts a nd e l imina t es t h e n e e d f o r a n ext e r n al b u f f er o p a m p . ta ble 12. refer e nce co nfi g ura t i o n summa r y reference operating mode input span (vinaCvi nb) (v p-p) require d vref (v) connect to internal 1.6 1 sense vref internal 4.0 2.5 sense refcom internal 1.6 span 4.0 and 1 vref 2.5 a n d r1 vref and se nse span = 1.6 vr ef vref = (1+r1/r 2 ) r2 sense and r e fc om exte rnal 1.6 span 4.0 1 vref 2.5 sense avdd vref ext. ref.
ad9260 rev. c | page 29 of 44 the ac t u a l r e fer e n c e v o l t a g es us e d b y t h e i n t e r n al cir c ui t r y o f th e ad9260 a p p e a r o n t h e capt an d cap b p i n s . i f vref is co nf igur ed f o r 2 . 5 v , th us p r o v idin g a 4 v f u l l -s cale in p u t s p a n , th e v o l t a g es a p p e a r a t capt and cap b a r e 3.0 v a nd 1.0 v r e s p e c t i ve l y . f o r p r o p er o p era t i o n w h e n usin g t h e in t e r n al o r a n e x te r n a l re fe re nc e, i t i s ne c e ss ar y to a dd a c a p a c i tor ne t w ork to de co u p le t h e c a pt and ca pb p i n s . f i gur e 67 sho w s t h e r e co mm e nde d de co u p ling ne t w o r k. thi s ca p a ci t i ve n e tw o r k pe rf o r m s th e f o llo w in g th r e e fun c ti o n s: (1) alo n g wi t h t h e r e fer e n c e a m pl i f ier , a2, i t p r o v i d es a lo w s o ur c e im p e dan c e o v er a la rg e f r e q uen c y ra n g e t o dr i v e t h e a/ d i n t e r n a l cir c ui t r y ; (2) i t p r o v ides t h e n e ces s a r y co m p ens a tio n f o r a2; and (3) i t b a ndlimi ts t h e n o is e con t r i b u t i o n f r o m t h e r e fer e n c e . th e t u r n - o n t i m e o f t h e refer e n c e vol t a g e a p p e a r i n g b e twe e n ca pt and capb is a p p r o x ima t e l y 15 m s and sh o u ld b e e v a l u a t e d in a n y p o w e r - do wn mo de o f o p er a t io n. capt capb ad9260 + + 10 f 0.1 f 10 f 0.1 f 0.1 f 0.1 f v ref sense refcom 00581-c-067 f i gure 67. rec o mmended refe r e nc e d e c o up ling ne t w ork
ad9260 rev. c | page 30 of 44 digital inputs and outputs digital outputs the ad9260 output data is presented in a twos complement format. table 13 indicates the output data formats for various input ranges and decimation modes. a straight binary output data format can be created by inverting the msb. table 13. output data format input (v) condition (v) digital output 8 decimation mode vinaCvinb < C0.8 vref 1000 0000 0000 0000 vinaCvinb = C0.8 vref 1000 0000 0000 0000 vinaCvinb = 0 0000 0000 0000 0000 vinaCvinb = +0.8 vref C 1 lsb 0111 1111 1111 1111 vinaCvinb >= + 0.8 vref 0111 1111 1111 1111 4 decimation mode vinaCvinb < C0.825 vref 1000 0001 0001 1100 vinaCvinb = C0.825 vref 1000 0001 0000 1100 vinaCvinb = 0 0000 0000 0000 0000 vinaCvinb = +0.825 vref C1 lsb 0111 1110 1110 0011 vinaCvinb >= + 0.825 vref 0111 1110 1110 0011 2 decimation mode vinaCvinb < C0.825 vref 1000 0000 0100 0001 vinaCvinb = C0.825 vref 1000 0000 0100 0001 vinaCvinb = 0 0000 0000 0000 0000 vinaCvinb = +0.825 vref C1 lsb 0111 1111 1011 1110 vinaCvinb >= + 0.825 vref 0111 1111 1011 1110 the slightly different full-scale input voltage conditions and their corresponding digital output code for the 4 and 2 decimation modes can be attributed to the different digital scaling factors applied to each ad9260 fir decimation stage for filter optimization purposes. thus, a + full-scale reading of 0111 1111 1111 1111 and C full-scale reading of 1000 0000 0000 0000 is unachievable in the 2 and 4 decimation modes. as a result, a digital overrange condition can never exist in the 2 or the 4 decimation mode and thus otr being set high indicates an overrange condition in the analog modulator. the output data format in 1 decimation differs from that in 2, 4 and 8 decimation modes. in 1 decimation mode the output data remains in a twos complement format, but the digital numbers are scaled by a factor of 7/128. this factor of 7/128 is the product of an internal scale factor of 7/8 in the analog modulator and a 1/16 scale factor caused by lsb justification of the 12-bit modulator data. cs and read pins the cs and read pins control the state of the output data pins (bit1Cbit16) on the ad9260. the cs pin is active low and the read pin is active high. when cs and read are both active the adc data is driven on the output data pins, otherwise the output data pins are in a high-impedance (hi-z) state. table 14 indicates the relationship between the cs and read pins and the state of pins bit 1 to bit 16. table 14. cs and read pin functionality cs read condition of data output pins low low data output pins in hi-z state low high adc data on output pins high low data output pins in hi-z state high high data output pins in hi-z state dav pin the dav pin indicates when the output data of the ad9260 is valid. digital output data is updated on the rising edge of dav. the data hold time (t h ) is dependent on the external loading of dav and the digital data output pins (bit1Cbit16) as well as the particular decimation mode. the internal dav driver is sized to be larger than the drivers pertaining to the digital data outputs to ensure that rising edge of dav occurs before the data transitions under similar loading conditions (i.e., fanout) regardless of mode. note that minimum data hold (t h ) of 3.5 ns is specified in the figure 4 timing diagram from the 50% point of davs rising edge to the 50% of data transition using a capacitive load of 20 pf for dav and bit1Cbit16. applications interfacing to ttl logic and/or having larger capacitive loading for dav than bit1Cbit16 should consider latching data on the falling edge of dav since the falling edge of dav occurs well after the data has transitioned in the case of the 2, 4, and 8 modes. the duty cycle of dav is approximately 50% and it remains active independent of cs and read. reset pin the reset pin is an asynchronous digital input that is active low. upon asserting reset low, the clocks in the digital decimation filters are disabled, the dav pin goes low and the data on the digital output data pins (bit 1Cbit 16) is invalid. in addition, the analog modulator in the ad9260 and internal clock dividers used in the decimation filters are reset and will remain reset as long as reset is maintained low. in the 2, 4, or 8 mode, the reset must remain low for at least a clock period to ensure all the clock dividers and analog modulator are reset. upon bringing reset high, the internal clock dividers will begin to count again on the next falling edge of clk and dav will go high approximately 15 ns after this falling edge, resuming normal operation. refer to figure 9 for a timing diagram. the state of the internal decimation filters in the ad9260 remains unchanged when reset is asserted low. consequently, when reset is pulsed low, this resets the analog modulator but does not clear all the data in the digital filters. the data in the filters is corrupted by the effect of resetting the analog modulator (this causes an abrupt change at the input of the digital filter and this change is unrelated to the signal at the input of the a/d converter). similarly, in multiplexed
ad9260 rev. c | page 31 of 44 applications in which the input of the a/d converters sees an abrupt change, the data in the analog modulator and digital filter will be corrupted. for this reason, following a pulse on the reset pin, or change in channels (i.e., multiplexed applications only), the decimation filters must be flushed of their data. these filters have a memory length, hence delay, equal to the number of filter taps times the clock rate of the converter. this memory length may be interpreted in terms of a number of samples stored in the decimation filter. for example, if the part is in 8 decimation mode, the delay is 321/f clock . this corresponds to 321 samples stored in the decimation filter. these 321 samples must be flushed from the ad9260 after reset is pulsed high prior to reusing the data from the ad9260. that is, the ad9260 should be allowed to clock for 321 samples as the corrupted data is flushed from the filters. if the part is in 4 or 2 decimation mode, then the relatively smaller group delays of the 4 and 2 decimation filters result fewer samples that must be flushed from the filters (108 samples and 23 samples respectively). in 2, 4, or 8 mode, reset may be used to synchronize multiple ad9260s clocked with the same clock. the decimation filters in the ad9260 are clocked with an internal clock divider. the state of this clock divider determines when the output data becomes available (relative to clk). in order to synchronize multiple ad9260s clocked with the same clock, it is necessary that the clock dividers in each of the individual ad9260s are all reset to the same state. when reset is asserted low, these clock dividers are cleared. on the next falling edge of clk following the rising edge of reset , the clock dividers begin counting and the clock is applied to the digital decimation filters. otr pin the otr pin is a synchronous output that is updated each clk period. it indicates that an overrange condition has occurred within the ad9260. ideally, otr should be latched on the falling edge of clk to ensure proper setup-and-hold time. however, since an overrange condition typically extends well beyond one clock cycle (i.e., does not toggle at the clk rate). otr typically remains high for more than a clock cycle, allowing it to be successfully detected on the rising edge of clk or monitored asynchronously. an overrange condition must be carefully handled because of the group delays in the low-pass di gital decimation filters in the output stages of the ad9260. when the input signal exceeds the full-scale range of the converter, this can have a variety of effects upon the operation of the ad9260, depending on the duration and amplitude of this overrange condition. a short duration overrange condition (<< filter group delay) may cause the analog modulator to briefly overrange without causing the data in the low pass digital filters to exceed full scale. the analog modulator is actually capable of processing signals slightly (3%) beyond the full-scale range of the ad9260 without internally clipping. a long duration overrange condition will cause the digital filter data to exceed full scale. for this reason, the otr signal is generated using two separate internal out-of- range detectors. the first of these out-of-range detectors is placed at the output of the analog modulator and indicates whether the modulator output signal has extended 3% beyond the full-scale range of the converter. if the modulator output signal exceeds 3% beyond full scale, the digital data is hard-limited (i.e., clipped) to a number that is 3% larger than full scale. due to the delay of the switched capacitor analog modulator, the otr signal is delayed 3 1/2 clock cycles relative to the clock edge in which the overranged analog input signal was sampled. the second out-of-range detector is placed at the output of the stage three decimation filter and detects whether the low pass filtered data has exceeded full scale. when this occurs, the filter output data is hard limited to full scale. the otr signal is a logical or function of the signals from these two internal out- of-range detectors. if either of these detectors produces an out- of-range signal, the otr pin goes high and the data may be seriously corrupted. if the ad9260 is used in a system that incorporates automatic gain control (agc), the otr signal may be used to indicate that the signal amplitude should be reduced. this may be particularly effective for use in maximizing the signal dynamic range if the signal includes high-frequency components that occasionally exceed full scale by a small amount. if, on the other hand, the signal includes large amplitude low frequency components that cause the digital filters to overrange, this may cause the low pass digital filter to overrange. in this case the data may become seriously corrupted and the digital filters may need to be flushed. see the reset pin function description above for an explanation of the requirements for flushing the digital filters. otr should be sampled with the falling edge of clk. this signal is invalid while clk is high. mode operation the mode select pin (mode) allows the user to select one of four available digital filter modes using a single pin. each mode configures the internal decimation filter to decimate at: 1, 2, 4, or 8. refer to table 15 for mode pin ranges. the mode selection is performed by using a set of internal comparators, as illustrated in figure 68, so that each mode corresponds to a voltage range on the input of the mode pin. the output of the comparators are fed into encoding logic where, on the falling edge of the clock, the encoded data is latched.
ad9260 rev. c | page 32 of 44 ta ble 15. reco mme nd ed mo d e pi n ra nges a nd co n f i g ura t i o ns mode pin rang e typical mode pin decimation mode 0 vC0.5 v gnd 8 0.5 vC1.5 v vref/2 2 1.5 vC3.0 v cml 4 3.0 vC5.0 v avdd 1 bias pin operation the bias s e le c t p i n (bi a s) g i v e s t h e us er , w h o is a b le t o o p er a t e th e ad9260 a t a s l o w er c l o c k ra te , t h e added f l exi b il i t y o f r u nnin g t h e de v i ce i n a lo w e r , p o w e r co n s u m p t i o n mo de w h en i t is c l o c k e d a t l e s s tha n 20 m h z. this is accom p l i s h e d b y s c alin g th e b i as c u r r en t o f th e ad9260 as il l u s t ra t e d in f i gur e 69. th e b i as a m p l if ier dr i v es a s o ur ce fol l o w er and fo r c es 1 v ac r o ss r ext , w h ich s e ts t h e b i as c u r r en t. this ef fe c t i v e l y ad j u s t s t h e b i as c u r r en t in t h e m o d u l a t o r a m plif iers an d fl as h p r e a m p lif i ers. w h e n a l a rg e val u e o f r ex t is us e d , a smal le r b i as c u r r en t is a v a i la b l e t o t h e in t e r n al a m plif ier cir c ui t r y . a s a r e su l t t h es e a m pl if iers n e e d m o r e t i m e t o s e t t le , t h us di c t a t i n g t h e us e o f a s l o w er clo c k as t h e p o w e r is r e d u ced . ref e r t o th e c h a r ac ter i za t i o n c u r v es s h o w n in f i gur e 47 t o f i gur e 54 r e v e alin g t h e p e r f o r ma n c e tradeo f f s. the s c ali n g is acco m p lish e d b y p r o p erl y a t t a chi n g a n ext e r n al r e sis t o r t o th e bi as p i n o f t h e ad9260 as sh o w n in t a b l e 17. r ext is n o r m a l ly 2 k? fo r a clo c k sp e e d o f 20 mh z and s c a l es in vers e l y wi t h cl o c k ra te . b e c a us e bi as is a n ex ter n a l p i n, mini mi za t i o n of ca p a ci t a nce to t h is p i n is r e co mmende d i n o r der t o p r e v en t in st ab i l i t y o f t h e b i as p i n am pli f ier . avdd 4r 3r 2r r mode pin avss e ncode r latch clock encoded mode 00581-c-068 f i g u re 68. si mpl i f i e d m o de p i n ci r c u i t r y bias current rext bias pin 1v 00581-c-069 f i g u re 69. si mpl i f i e d bi as p i n ci r c u i t r y
ad9260 rev. c | page 33 of 44 power dissipation considerations the p o wer dis s i p a t io n o f t h e ad9260 is dep e nden t on i t s a p plic a t ion sp e c if ic co nf igura t ion an d op era t i n g co n d i t ion s . the a n a l o g p o wer dissi p a t io n as sho w n i n f i gur e 70 is p r ima r i l y a f u n c t i o n o f i t s p o w e r b i as s e t t in g a nd s a m p le ra t e . i t r e main s in s e n s i t i v e t o t h e p a r t ic u l a r in pu t w a v e fo r m b e i n g dig i t i ze d o r dig i t a l f i l t er mode s e t t in g . t h e dig i t a l p o w e r dissi p a t io n is p r ima r il y a f u n c t i o n o f t h e dig i t a l s u p p l y s e t t in g (i .e ., +3 v t o +5 v), t h e s a m p le ra t e and , t o a les s er ext e n t , t h e mo d e s e t t i n g a nd i n p u t wa vefo r m . f i gur e 71 a nd f i gur e 72 sh o w t h e to t a l c u r r en t diss i p a t io n o f t h e com b in e d dig i t a l (d vdd) a nd dig i t a l dr ive r su p p ly ( d r v dd ) for + 3 v and + 5 v sup p l i e s . n o te, d v dd and dr vdd a r e ty p i ca l l y der i ve d f r o m t h e s a me su p p ly b u s s i nc e no d e g r a d a t i o n i n p e r f or m a nc e re su lt s . a 1 m h z f u l l - s c ale sine wa v e was us e d t o e n sur e maxim u m dig i tal ac tivi ty in t h e dig i t a l f i lters a nd t h e dig i t a l dr i v ers had a fan o u t o f on e. n o te a l s o t h a t a tw o f old de cr e a s e in dig i t a l su p p ly c u r r en t re su l t s w h e n t h e dig i t a l su p p ly is re d u c e d for m + 5 v to + 3 v . 30 50 70 90 110 130 i av dd (ma) sample rate (msps) 51 5 10 20 00581-c-070 quarter bias [8k ? ] full bias [2k ? ] half bias [4k ? ] f i g u re 70. i av d d v s . s a mp le rate (a vdd = + 5 v , mod e 1x-4x) 0 2 4 6 8 10 i dv dd /i drv dd (ma) 12 14 16 sample rate (msps) 5 1 5 10 20 00581-c-071 8 mode 4 mode 2 mode 1 mode f i gure 71. idvdd / i d r v dd vs. s a mp le rate (dvdd = dr v dd = 3 v , f in = 1 mh z) 0 5 10 15 20 25 30 i dv dd /i drv dd (ma) sample rate (msps) 51 5 10 20 00581-c-072 8 mode 4 mode 2 mode 1 mode f i g u re 72. i dvdd /i dr vd d vs. s a mp le rate ( d vdd = dr vdd = 5 v , f in = 1 mhz) digi tal ou tput dri v e r consi d eratio ns (dr v d d ) the ad9260 ou t p u t dr i v ers can be co nf igur e d to in t e r f ac e wi t h +5 v o r 3.3 v log i c fa milies b y s e t t in g d r vd d t o +5 v o r 3.3 v , r e s p ec ti ve l y . the ad9260 o u t p u t dr i v ers in each m o de a r e a p p r o p r i a t e l y size d t o p r o v i d e suf f i cien t o u t p u t c u r r en t t o dr i v e a w i de va r i e t y o f log i c fa mi lies. h o w e v e r , la rg e dr i v e c u r r en ts t e nd t o c a us e g l i t ch es on t h e su pplies a nd ma y a f fe c t s i n a d p e r f o r ma n c e . a p plica t io n s r e q u ir in g t h e ad92 60 t o dr i v e la rge ca p a ci t i v e lo ads o r la rg e fa n o u t ma y r e q u ir e addi tio n al de co u p ling ca p a ci to rs o n dr v d d . the ad di t i o n o f ex ter n a l b u f f ers o r la t c h e s he l p s r e d u ce ou t p u t lo ading w h ile p r o v idin g ef fe c t i v e is ola t ion f r o m t h e da t a b u s. c l ock i n p u t a n d c o ns id er at ions the ad9260 in t e r n al timin g us es th e tw o e d g e s o f th e c l o c k in p u t t o ge n e ra te a va r i e t y o f in ter n a l t i min g sig n a l s. th e clo c k i n p u t m u s t m eet o r e x ceed th e m i n i m u m s p ecif i e d p u l s e w i d t h hig h and lo w (t ch a nd t cl ) sp e c if ica t io n s fo r t h e g i v e n a / d as def i n e d i n t h e s w i t chi n g s p e c if ica t io ns a t t h e b e g i nni n g o f t h e da t a sh e e t t o me et t h e ra t e d p e r f o r ma n c e s p e c if ica t io n s . f o r exa m p l e , t h e c l o c k in p u t t o t h e ad9260 o p era t in g a t 20 ms ps m a y h a v e a d u t y c y c l e be t w een 45% a n d 55% t o m eet th i s t i mi n g r e q u ir e m e n t si n c e t h e mini m u m sp e c i f ie d t ch an d t cl is 22.5 n s . f o r c l o c k ra t e s b e lo w 2 0 ms ps, t h e d u ty c y c l e ma y de v i a t e f r o m t h i s ra n g e t o t h e e x t e n t t h a t b o t h t ch a nd t cl are sa ti s f i e d . a l l h i g h s p ee d , hi gh r e so l u ti o n a/ d s a r e se n s i t i v e t o t h e q u ali t y o f t h e clo c k i n p u t. th e deg r ada t io n in snr a t a gi v e n full - s c a l e i n p u t f r eq u e n c y (f in ) d u e to on l y a p e r t u re j i tte r (t a ) ca n be calc u l a t e d wi th t h e f o l l o w in g eq ua t i o n : ( ) [ ] a in t f snr = 2 / 1 log 20 10 i n t h e e q u a t i on, t h e r m s a p er t u r e ji t t er , t a , r e p r es en ts t h e r o o t s u m s q ua r e o f al l th e ji t t er s o ur ces which inc l ude t h e c l o c k in p u t, a n a l og i n p u t sig n a l , and a/d a p er t u r e ji t t e r sp e c if ic a t ion . f o r exa m p l e , if a 500 kh z f u l l -s cale sin e wa ve is s a m p led b y a n
ad9260 rev. c | page 34 of 44 a/d w i t h a t o t a l r m s ji t t er o f 15 ps, t h e snr p e r f o r ma n c e o f t h e a/d wil l be l i mi t e d t o 86.5 db . the clo c k in pu t sh o u l d b e t r e a te d as a n ana l og sig n a l i n cas e s w h er e a p er t u r e ji t t er ma y a f fe c t t h e d y namic ran g e o f t h e ad9260. i n fac t , th e clk in p u t b u f f er is in t e r n a l l y p o w e r e d f r o m th e ad92 60 s a n alog s u p p l y , a v d d . th u s th e clk log i c hig h and lo w in p u t v o l t a g e le v e l s a r e +3.5 v a nd + 1 . 0 v , re sp e c t i vely . s u p p l ies fo r c l oc k dr i v ers s h o u l d b e s e p a ra t e d f r o m the a/d o u t p ut dr i v er s u p p lies t o a v o i d m o d u l a t i n g t h e clo c k sig n al w i t h dig i t a l n o is e. l o w ji t t er cr ys t a l co n t r o l l e d os ci l l a t o r s mak e t h e b e st clo c k s o ur c e s. i f t h e clo c k i s gen e ra t e d f r o m an o t h e r ty p e o f s o u r c e ( b y g a t i n g , d i v i d i n g , or ot he r me t h o d ) , it shou l d b e r e t i m e d b y t h e o r ig ina l clo c k a t t h e last st e p . grounding and decoupling analog and di gital g r ou ndi n g p r o p er g r o u n d in g is es s e n t ial in an y hig h s p ee d , hig h r e s o l u tio n sys t em. m u l t i l a y er p r in t e d cir c ui t b o a r ds (pcbs) a r e r e co mm e nde d to p r o v ide op t i m a l g r o u n d in g and p o w e r s c he me s . t h e u s e of g r ou nd a n d p o we r p l a n e s of f e r s dist i n c t adva n t ages: 1. t h e m i n i m i z a t i on of t h e l o op a r e a e n c o m p a s s e d b y a s i g n a l a nd i t s r e t u r n p a t h . 2. t h e m i n i m i za tio n o f th e im pe da n c e as socia t e d w i th gr o u n d a n d po w e r pa th s . 3. the in her e n t di st r i b u te d c a p a ci to r fo r m e d b y t h e p o w e r pla n e, pcb in su la t i on, and g r o u nd plan e. the s e char ac te r i st ic s re su l t i n b o t h a re d u c t ion of e l e c t r o m a g n e t i c in t e r f er ence (e mi) a n d an o v e r al l i m p r o v em en t i n pe rf o r m a n c e . i t is im p o r t a n t to desig n a la yo u t tha t p r ev en ts n o is e f r o m co u p lin g o n t o t h e in p u t sig n al. dig i t a l sig n als sh o u ld n o t b e r u n in p a ra l l e l w i t h in p u t sig n a l t r a c es a nd sh o u ld b e r o u t e d a w a y f r o m th e in p u t cir c ui tr y . w h ile th e ad9260 f e a t ur es s e p a ra t e a n a l o g a nd d i g i t a l g r o u n d pin s , i t sh o u ld b e t r e a te d as an a n a l o g co m p on en t. the a v ss, d v ss a n d d r vss p i n s m u s t b e j o i n e d t o ge ther d i r e c t l y u n d e r the ad92 60. a s o lid g r o u nd plan e u nder t h e a/ d is acce p t a b le if t h e p o w e r a nd g r o u nd r e t u r n c u r r en t s a r e ma na ge d car e f u l l y . al ter n a t i vely , t h e g r o u nd plan e u nder th e a / d m a y co n t a i n se rra t i o n s t o ste e r c u r r en t s in p r e d ic t a b l e dir e c t io n s w h ere cr o s s-co u p ling b e tw e e n a n a l o g a nd d i g i t a l w o u l d o t h e r w is e be u n a v o i da b l e . th e ad9260/eb g r o u n d la yo u t , sh o w n i n f i gur e 83, depic t s t h e s e r r a t e d ty p e o f a r r a n g em e n t. t h e a n a l o g a nd d i g i t a l g r o u n d s ar e co nn e c te d b y a j u m p er b e lo w t h e a/d . analog and di gital su pply d e co upling the ad9260 f e a t ur es s e p a ra t e a n alog, dig i t a l , a nd dr i v er su p p l y a nd g r o u nd p i ns, hel p i n g to m i nimi z e d i g i t a l c o r r u p t i o n o f sen s i t i v e a n alog si gn als. fi g u r e 7 3 s h ow s t h e p o w e r s u pp l y r e j e c t i o n r a t i o v s . f r e q u e n c y f o r a 200 mv p-p r i p p le a p p l ie d t o a v d d , d v d d , a nd da v d d. 40 45 50 55 60 65 70 75 80 85 90 p s rr (dbfs ) frequency (khz) 10 1 01 0 2 10 3 10 4 00581-c-073 avdd dvdd and drvdd f i gur e 7 3 . ad92 60 p s rr vs . f r e q ue nc y (8 x mo de ) i n ge ne r a l, a v dd , t h e ana l o g su p p ly , s h ou l d b e de c o u p l e d to a v ss, t h e a n alo g co mm on, as cl os e t o t h e chi p as ph ysical l y p o ssi b le. f i gur e 74 sho w s t h e r e co mm e nde d de co u p lin g fo r t h e a n alog s u p p lies; 0.1 f cera mic c h i p c a p a ci t o rs s h o u l d p r o v ide a d e q u a t e ly l o w i m p e d a nc e o v e r a w i d e f r e q u e nc y r a nge. n o te tha t t h e a v d d a nd a v ss p i n s a r e co-lo c a t ed on t h e ad9260 to sim p lif y t h e l a yo u t o f t h e de co uplin g c a p a ci t o rs a nd p r o v ide t h e shor te st p o ss ibl e p c b t r ac e l e ng t h s . t h e a d 9 2 6 0 / e b p o we r p l a n e l a y o ut , s h ow n i n fi g u r e 8 4 d e pi c t s a t y pi c a l a r r a n g e m e n t usin g a m u l t il a y er pcb . 00581-c-074 avdd avss ad9260 avdd avss 0.1 f 0.1 f 0.1 f avdd avss 4 3 28 29 38 44 f i g u re 74. a n a l og s u p p ly d e coup ling the dig i t a l ac t i v i ty o n t h e ad92 60 chi p fa l l s i n to tw o gen e ra l ca tego r i es: dig i t a l lo g i c a n d ou tp u t dr i v ers. t h e in ter n a l d i g i t a l log i c dra w s s u rg es o f c u r r en t, ma inl y d u r i n g t h e clo c k tra n si tio n s. th e o u t p u t dr i v ers dra w la rg e c u r r en t im p u ls es w h i l e t h e o u t p ut b i ts a r e cha n g i n g . the si ze and d u r a t i o n o f t h es e c u r r en ts ar e a f u n c t i o n o f t h e lo ad o n t h e o u t p ut b i ts: la rg e ca p a ci t i v e lo ads a r e t o be a v o i de d . n o t e tha t t h e dig i tal log i c o f
ad9260 rev. c | page 35 of 44 th e ad9260 is ref e r e n c ed d v dd whil e t h e o u t p u t dr i v ers a r e re fe re nc e d to d r v d d . a l s o no te t h a t t h e sn r p e r f or m a nc e o f th e ad9260 r e ma in s in dep e nden t o f t h e dig i t a l o r dr i v er su p p ly s e tt ing . the deco u p l i n g s h o w n in f i gur e 75, a 0.1 f cera mic c h i p ca p a ci t o r , is a p pr o p r i a t e fo r a r e as o n a b le c a p a ci t i ve lo ad o n t h e dig i t a l o u t p uts (ty p ic a l ly 20 pf o n e a ch pin). a p plica t io n s in v o lvin g g r e a t e r dig i t a l lo ads sh o u ld con s ider in cr e a s i n g t h e d i g i t a l d e c o upl i ng prop or t i on a l ly , an d / or u s i n g e x te r n a l bu f f e r s / l a t c h e s . 0.1 f 0.1 f dvdd dvss ad9260 drvdd drvss 3 1 6 5 00581-c-075 f i g u re 75. d i g i t a l s u p p ly d ecoup ling a co m p lete de c o u p lin g s c h e me wil l als o in c l u d e la rg e ta n t al u m o r e l ec tr ol ytic ca p a ci t o rs o n the pcb t o r e d u ce lo w f r eq uen c y r i p p le t o neg l ig ib le leve ls. ref e r t o th e ad9260 /eb s c h e ma tic a nd l a yo u t s in f i gur e 80 t o f i gu r e 84 f o r m o r e inf o r m a t io n re g a rd i n g t h e p l a c e m e n t of d e c o up l i ng c a p a c i t o r s . an al t e r n a t i v e l a yo u t an d decou p lin g s c h e me is s h o w n in f i gu r e 7 6 . t h i s la y o u t a n d d e c o u p li n g sc h e m e i s w e ll s u i t e d f o r a p p l ic a t io n s in which m u l t i p le ad9260s a r e lo ca t e d o n the s a m e pc bo a r d a nd/o r t h e ad9 260 is p a r t o f a m u l t ic a r d mixe d-sig n al sys t em in which g r o u n d s a r e tie d bac k a t t h e sys t em s u p p lies (i .e ., s t a r g r o u nd co nf igura t ion). i n t h is cas e , th e ad9260 is t r ea t e d as a n a n a l og co m p o n en t in which i t s a n alog (i .e ., a v d d ) a nd digi t a l (d vd d and d r vd d) s u p p lies are de r i ve d f r om t h e s y ste m s + 5 v ana l o g su p p ly and a l l of t h e ad9260 s g r o u nd p i n s a r e t i ed dir e c t l y t o t h e analog g r o u n d pla n e w h ich r e s i des d i r e c t ly under n e a t h t h e i c . refer r i n g to f i g u r e 76, e a ch supply p i n is dir e c t ly de co u p le d to t h e i r re sp e c t i v e g r ou nd pi n or a n a l o g g r ou nd pl ane v i a a cera mic 0.1 f c h i p c a p a ci t o r . s u r f ace m o u n t fer r i t e b e ads a r e us e d to is ol a t e t h e a n a l o g (a vdd), dig i t a l ( d v d d), a nd dr i v er s u p p lies (d r v d d ) o f th e ad9 260 f r o m th e +5 v p o w e r b u s. p r o p erl y s e le c t e d fer r i t e b e ads c a n p r o v ide m o re t h a n 40 db o f is ola t ion f r o m h i g h f r e q ue n c y swi t chi n g t r a n sie n ts o r ig in a t i n g f r o m ad9260 su p p l y p i n s . f u r t h e r n o is e imm u ni ty f r o m n o is e is p r o v id e d b y t h e in h e r e n t p o w e r su p p ly r e j e c t io n o f t h e ad9260 as sh o w n in f i gur e 70 . i f dig i tal op era t io n a t 3 v is d e sira b l e f o r p o w e r sa vin g s an d o r t o p r o v id e f o r a 3 v d i g i tal l o g i c i n te r f a c e, a 5 v to 3 v l i ne ar re g u l a tor c a n b e u s e d to dr i v e d v dd a n d / or dr v d d . a mo re c o m p l e te d i s c u s s i on on t h i s la yo u t and de cou p lin g s c h e me c a n b e fo und i n c h a p ter 7, p a ges 7-27 t o 7-55 o f th e h i g h sp eed desig n t e c h niq u es s e mina r b o ok, w h ich is a v a i lab l e a t : w w w . a na log . co m/s u ppo r t / f r a m e s /l i n _f r a m e se t. h m l ferrite bead core* v a sampling clock generator ad9260 0.1 f 0.1 f 10 f 0.1 f 0.1 f 0.1 f dvdd dvss avdd avss avdd avss avdd avss drvdd drvss clk buffer latch bits 1?16, da v v a insert 5/3 volt linear regulator for 3 or 3.3v digital operation 00581-c-076 f i gu r e 7 6 . hi gh f r equ e n c y s u ppl y re jecti o n
ad9260 rev. c | page 36 of 44 evaluation board gene ral description the ad9260 e v al ua tio n b o a r d is de sig n ed t o p r o v ide an easy a nd f l exi b le m e t h o d o f exer cisin g th e ad9260 and dem o ns tra t e i t s pe rf o r m a n c e t o da ta s h ee t s p eci f i c a t i o n s . th e ev al ua ti o n bo a r d is fab r ic a t ed in f o ur la yers: th e co m p on en t la yer , t h e g r o u n d la yer , t h e p o w e r l a yer , a nd t h e s o lder la yer . th e b o a r d i s c l ea r l y l a be l e d t o p r o v i d e ea s y i d e n t i f i ca t i o n o f co m p o n en t s . am ple s p ace is p r o v ide d n e a r t h e a n alog a nd cl o c k i n p u ts t o p r o v i d e a d d i t i o n al o r al t e rn a t e si gn al co n d i t i o ni n g . features and user controls jumper controlled mo de/osr selection the ch o i ce o f m o de/os r can easil y be va r i e d b y j u m p in g ei t h er jp1, jp2, jp3, o r jp4 as il l u s t ra t e d in f i gur e 78 wi thin t h e m o de/ o s r c o n t r o l blo c k. t o ob t a i n t h e desir e d m o d e , r e fer to t a b l e 16. table 16. a d 9 260 evaluation board mode s e lect mode/osr connect ju mper 1 jp4 2 jp2 4 jp3 8 jp1 select able po wer bi as the p o wer co n s um p t ion o f the ad9260 can be s c ale d do wn if t h e us er is ab le to o p era t e t h e de vice a t a lo w e r clo c k f r e q uen c y . a s il l u s t ra t e d in f i gur e 78, p i n c u ps a r e p r o v ide d f o r th e ext e r n al r e sis t o r (r2) tied t o t h e b i as p i n o f the ad9260. t a b l e 17 def i n e s t h e r e co m m e nde d r e sist an ce fo r a g i ven clo c k s p eed t o o b ta i n th e d e si r e d po w e r co n s um p t i o n. ta ble 17. e v a l u a t i on boa r d re comme nde d r e s i s t a n ce va lue for extern al bias resistor resistor val u e clock speed (m ax) power consumption 2 k? 20 mhz 585 mw 4 k? 10 mhz 325 mw 8 k? 5 mhz 200 mw 16 k? 2.5 mhz 150 mw dat a inte rfaci n g controls the da t a i n t e r f acin g co n t r o ls (res etb , cs b , r e ad , d a v) a r e al l acces s ib le via s m a co nn ec t o rs ( j 2Cj5) as il l u s t ra t e d in f i gur e 78 wi thin t h e da ta in t e r f acin g con t r o l b l o c k. th e r e s e tb , c s b , a n d r e ad co nn ecti o n s a r e ea ch s u p p l i ed wi t h tw o s e ts o r r e sist o r p i n c u ps t o a l lo w t h e us er to p u l l -u p o r p u l l - do wn e a ch sig n a l to a f i xe d st a t e. r5, r6, and r 30 wi l l ter m ina t e t o g r o u n d , whil e r7, r28, and r29 t e r m ina t e to d r vd d . th e d a v and otr sig n a l s a r e a l s o dir e c t ly co n n e c te d to t h e d a t a o u t p ut co n n e c to r p1. al l in t e r f acin g con t r o ls a r e b u f f er e d thr o ug h t h e cm os line dr i v er 74h c541. bu ffe r ed ou tpu t d a ta t h e tw os co m p le m e n t o u t p u t da ta i s b u f f e r ed th r o ugh tw o cmos n o n i n v e r t i n g b u s t r a n s c ei vers (u2 an d u3) a nd ma de a v a i la b l e a t pin co nn e c to r p1 as i l l u st r a te d in f i gur e 78 wi t h i n th e da t a o u t p u t b l oc k . jumper controlled reference source the ch o i ce o f r e f e r e n c e f o r th e ad9260 can eas i l y be va r i e d betw een 1.0 v , 2 . 5 v o r ext e r n al b y usin g j u m p ers jp5, jp6, jp7, an d j p 9 a s i l lu st r a te d i n fi g u re 7 8 w i t h i n t h e re f e re nc e co nf igur a t io n b l o c k. t o ob t a i n t h e desir e d r e fer e n c e, s e e t a b l e 18. ad817r c1 5 0.1 f c1 7 10 f r11 49.9 ? jp10 r12 15k ? r13 10k ? r3 15k ? r4 10k ? r1 0 1k ? vcc2 u6 c14 r8 390 ? r9 1k ? q1 2n2222 c12 c 1 3 10 f + 2.5/3v nc vout trim nc +vin temp gnds ad780r u5 c18 0.1 f 0.1 f 0.1 f 0.1 f c19 vcc2 1 2 3 4 8 7 6 5 agnd agnd agnd vrefext 1kpot 1v + 00581-c-077 f i g u re 77. ev aluat i on b o a r d e x t e rn al r e f e r e n c e c i rcuit r y
ad9260 rev. c | page 37 of 44 table 18. evaluation board reference pin configuration reference voltage connect jumper input voltage (p-p fs) 2.5 v jp7 4.0 v 1.0 v jp6 1.6 v external jp5, jp9, and jp10 4.0 v the external reference circuitry is illustrated in figure 77. by connecting or disconnecting jp10, the external reference can be configured for either 1.0 v or 2.5 v. by connecting jp10, the external reference will be configured to provide a 2.5 v reference and by disconnecting jp10 reference, it will be configured for 2.5 v. by leaving jp10 open, the external reference will be configured to provide a 1.0 v reference. flexible dc or ac coupled external clock inputs as illustrated in figure 78, the ad9260 evaluation board is designed to allow the user the flexibility of selecting how to connect the external clock source. it is also equipped with a playpen area for experimenting with optional clock drivers or crystals. selecting dc or ac coupled external clock: dc coupled: to directly drive the clock externally via the clkin connector, connect jp11 and disconnect jp12. note: 50 ? terminated by r27. ac coupled: to ac couple the external clock and level shift it to midsupply, connect jp12 and disconnect jp11. note: 50 ? terminated by r27. flexible input signal configuration circuitry the ad9260 evaluation boards input signal configuration block is illustrated in figure 79. it is comprised of an input signal summing amplifier (u7), a variable input signal common-mode generator (u10), and a pair of amplifiers (u8 and u9) that configure the input into a differential signal and drive it, through a pair of isolation resistors, into the input pins of ad9260. the user can either input a signal or dual signal into the evaluation board via the two sma connectors (j6 and j7) labeled in-1 or in-2. the user should refer to the driving the input section of the data sheet for a detailed explanation of how the inputs are to be driven and what amplifier requirements are recommended. selecting single or dual signal input the input amplifier (u7) can either be configured as a dual input signal inverting summer or a single tone inverting buffer. this flexibility will allow for slightly better noise performance in the single tone mode due to the inherent noise gain difference in the two amplifier configurations. an optional feedback capacitor (c9) was added to allow the user additional out-of band filtering of the input signal if needed. for two-tone input signals: the user would leave jumpers (jp8) connected and use in-1 and in-2 (j7 and j6) as the connectors for the input signals. for signal tone input signal: the user would remove jumper (jp8) and use only in-1 as the input signal connector. selectable input signal common-mode level source the input signals common-mode level (cml) can be set by u10. to use the input cml generated by u10: disconnect jumper jp13 and connect resistors rx3 and rx4. the cml generated by u10 is variable and adjustable using the 1 k? variable resistor r35. shipment configuration the ad9260 evaluation board is configured as follows when shipped: 1. 2.5 v external reference/4.0 v differential full-scale input: jp5, jp9, and jp10 connected, jp6 and jp7 disconnected. 2. 8 mode/osr: jp1 connected, jp2, jp3, and jp4 disconnected. 3. full speed power bias: r2 = 2 k? and connected. 4. csb pulled low: r6 = 49.9 ? and connected, r29 disconnected. 5. resetb pulled high: r7 = 10 k? and connected, r30 disconnected. 6. read pulled high: r28 = 10 k? and connected, r5 disconnected. 7. single tone input: jp8 removed, input applied via in-1 (j7). 8. input signal common-mode level set by variable resistor r35 to 2.0 v: jumper jp12 is disconnected and resistors r4 and r3 are connected. 9. ac-coupled clock: jp12 connected and jp11 disconnected. note: 50 ? terminated by r27. quick setup 1. connect the required power supplies to the evaluation board as illustrated in figure 28: 5 va supplies to p5analog power +5 va supply to p4analog power +5 vd supply to p3digital power +5 vd supply to p2driver power 2. connect a clock source to clkin (j1): note: 50 ? terminated by r1. 3. connect an input signal source to the in-1 (j7). 4. tur n on p ower. 5. the ad9260 evaluation board is now ready for use.
ad9260 rev. c | page 38 of 44 application information 1. the adc analog input should not be overdriven. using a signal amplitude slightly lower than fsr will allow a small amount of headroom so that noise or dc offset voltage will not overrange the adc and hard limit on signal peaks. 2. two-tone tests can produce signal envelopes that exceed fsr. set each test signal to slightly less than C6 db to prevent hard limiting on peaks. 3. band-pass filtering of test signal generators is absolutely necessary for snr, thd, and imd tests. note that a low noise signal generator along with a high q band-pass filter is often necessary to achieve the attainable noise performance of the ad9260. 4. test signal generators must have exceptional noise performance to achieve accurate snr measurements. good generators, together with fifth-order elliptical band- pass filters, are recommended for snr tests. narrow bandwidth crystal filters can also be used to filter generator broadband noise, but they should be carefully tested for operation at high signal levels. 5. the analog inputs of the ad9260 should be terminated directly at the input pin sockets with the correct filter terminating impedance (50 ? or 75 ?), or it should be driven by a low output impedance buffer. short leads are necessary to prevent digital noise pickup. 6. a low noise (jitter) clock signal generator is required for good adc dynamic performance. a poor generator can seriously impair good snr performance particularly at higher input frequencies. a high frequency generator, based on a clock source (e.g., crystal source), is recommended. frequency-synthesized clock generators should generally be avoided because they typically provide poor jitter performance. see note 8 if a crystal-based clock generator is used during fft testing. a low jitter clock may be generated by using a high- frequency clock source and dividing this frequency down with a low noise clock divider to obtain the ad9260 input clk. maintaining a large amplitude clock signal may also be very beneficial in minimizing the effects of noise in the digital gates of the clock generation circuitry. finally, special care should be taken to avoid coupling noise into any digital gates preceding the ad9260 clk pin. short leads are necessary to preserve fast rise times and careful decoupling should be used with these digital gates and the supplies for these digital gates should be connected to the same supplies as that of the internal ad9260 clock circuitry (pins 44 and 38). 7. two-tone testing will require isolation between test signal generators to prevent imd generation in the test generator output circuits. 8. a very low-side lobe window must be used for fft calculations if generators cannot be phase-locked and set to exact frequencies. 9. a well designed, clean pc board layout will assure proper operation and clean spectral response. proper grounding and bypassing, short lead lengths, separation of analog and digital signals, and the use of ground planes are particularly important for high frequency circuits. multilayer pc boards are recommended for best performance, but if carefully designed, a two-sided pc board with large heavy (20 oz. foil) ground planes can give excellent results. 10. prototype plug-boards or wire-wrap boards will not be satisfactory.
ad9260 rev. c | page 39 of 44 tp7 t p9 tp11 tp12 tp13 p1 17 p1 19 p1 21 p1 23 p1 25 p1 27 p1 29 p1 31 p1 33 p1 38 p1 39 p1 37 p1 35 p1 2 p1 4 p1 6 p1 8 p1 10 p1 12 p1 14 p1 16 p1 18 p1 20 p1 22 p1 24 p1 26 p1 28 p1 30 p1 32 p1 34 p1 38 p1 40 p1 1 p1 3 p1 5 p1 7 p1 9 p1 11 p1 13 p1 15 20 10 18 17 16 15 14 1 19 2 3 4 5 6 7 8 9 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 22 21 20 19 18 34 35 36 37 38 39 40 41 42 17 16 15 14 13 12 12 3 456 78 91 01 1 33 32 31 30 29 28 27 26 25 24 23 43 44 13 12 11 rd tp1:r d tp8:otr drv dd vc c gnd y1 y2 y3 y4 y5 y6 y7 y8 u4 74h c 541 g1 g2 a1 a2 a3 a4 a5 a6 a7 a8 u2 74h c 245 dir a1 a2 a3 a4 a5 a6 a7 a8 gnd vc c out_en b1 b2 b3 b4 b5 b6 b7 b8 u3 74h c 245 drv dd drv dd drv dd drv dd tp10 jp15 ct 1 ct2 ct3 ct4 ct5 ct6 ct7 ct8 ct9 ct1 0 ct1 1 ct1 2 ct1 3 ct1 4 ct1 5 ct1 6 ct1 8 ct1 7 data output block j2 j3 j4 j5 r eset c s re ad dav drv dd r5 49.9 ? r2 8 10k ? r6 49. 9 ? r2 9 10k ? r3 0 49. 9 ? r7 10k ? data output control block jp5: ext r e f jp6: 1v r e f jp7: 2.5v r e f jp9: ext r e f mdav dd reference configuratio n block + c1 0 10 f 10 f 10 f 10 f c1 1 tp6 mdav dd jp4: 1 jp3: 4 jp2: 2 jp1: 8 mode/osr control block tp2 tp3 tp4:refb tp5:reft c5 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f c4 c2 r2 2k ? c1 c3 c6 c7 w1 w2 invdd dv dd flavdd ct2 0 c6 1 c 6 2 dv dd ct1 9 j1 clki n rd mo de re fcom bias cap b cap t a vss cm l nc vin a vin b nc av dd vr ef sen se r eset a vss av dd cs dav otr bit0 1 ( ms b) bit0 2 d vss a vss dv dd av dd d r vss drv dd clk re ad bit1 6 ( ls b) bit1 5 bit1 4 bit1 3 bit1 2 bit1 1 bit1 0 bit0 9 bit0 8 bit0 7 bit0 6 bit0 5 bit0 4 bit0 3 ad9260 cm l vin a vin b 1v cm l vr efext r2 7 49.9k ? c8 r3 3 1k ? jp13 jp11 r3 1 1k ? r esetb cs bbue tp15 agnd dc coup le d ac coup le d s h ie lde d _ t race nc = no conne ct mdav dd dir a1 a2 a3 a4 a5 a6 a7 a8 gnd vc c out_en b1 b2 b3 b4 b5 b6 b7 b8 00581-c-078 f i g u re 78. ev aluat i on b o a r d t o p l e ve l s c he m a t i c
ad9260 rev. c | page 40 of 44 ad817r 3 2 7 6 4 vcc2 c22 0.1 f 0.1 f c23 10 f + r32 390 ? rx4 xxx cx4 xxx r34 390 ? rx3 xxx c25 ikpot r35 1k ? jp12 9260cml u10 ad9632 3 2 8 7 6 5 4 vcc2 vee r26 390 ? u9 r25 390 ? jp17 ad9632 3 2 8 7 6 5 4 vcc2 vee r20 390 ? u8 jp16 r24 390 ? r23 390 ? r17 390 ? r19 390 ? c20 r18 390 ? r48 50 ? r46 50 ? c26 100pf r49 50 ? vinb c24 100pf r47 50 ? vina c16 100pf r16 390 ? r14 50 ? r22 390 ? c9 tbd jp8 r21 390 ? r1 57.6 ? r15 57.6 ? j6 j7 in-2 in-1 ad9632 2 3 5 4 6 8 7 vee vcc2 u7 0.1 f 00581-c-079 f i g u re 79. ev aluat i on b o a r d i n put co nf ig ur at ion bl ock c39 0.01 f c38 0.1 f r41 r40 l3 c37 0.1mf c36 10mf + c43 0.01 f c42 0.1 f r43 r42 l4 c41 0.1 f c40 10 f + c47 0.01 f c46 0.1 f r45 r44 l5 c45 0.1 f c44 10 f + p4:+5v 1 p4 2 c35 0.01 f c34 0.1 f r39 r38 l2 c33 0.1 f c32 22 f + p3 2 p3:d5 1 evaluation board power supply configuration p2:vdd 1 c28 + r37 r36 l2 c29 p2 2 c30 c31 c64 c48 c49 c50 vee vee vee vcc2 vcc2 vcc2 u7 u8 u9 u7 u8 u9 device supply decoupling flavdd mdavdd invdd dvdd drvdd p5:+5aux 1 c27 47 f + r51 r50 l6 c55 p5 2 vcc2 p5:? 5aux 1 c56 47 f 47 f + r53 r52 l7 c57 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f p5 2 vee c51 c52 c53 c54 vcc2 drvdd drvdd drvdd u10 u2 u3 u4 00581-c-080 f i g u re 80. ev aluat i on b o a r d p o wer s u p p ly conf ig ur at i o n and coup ling
ad9260 rev. c | page 41 of 44 f i g u re 81. ev aluat i on b o a r d co mpo n ent sid e lay o ut (n ot to s c a l e) f i g u re 82. ev aluat i on b o a r d s o lde r s i de layo ut (not to s c a l e)
ad9260 rev. c | page 42 of 44 f i g u re 83. ev aluat i on b o a r d g r ound plan e lay o ut (n ot to s c al e) f i g u re 84. ev aluat i on b o a r d p o wer pl ane l a yout ( n ot t o s c a l e)
ad9260 rev. c | page 43 of 44 outline dimensions 0. 80 bs c 0. 45 0. 29 2. 4 5 ma x 1. 03 0. 88 0. 73 sea t i n g pl a n e to p v i e w (p i n s d o w n ) 1 33 34 11 12 23 22 44 c o p l an ari t y 0. 10 pi n 1 0. 25 m a x 0. 10 m i n view a rotated 90 ccw 7 0 2.20 2.00 1.80 view a 13. 45 13. 20 s q 12. 95 10. 20 10. 00 s q 9. 80 compliant to jedec standards ms-022ab - f i g u re 85. 44-l e ad m qfp (s-44) d i m e nsi o ns sh o w n in m i l l i m eters and inch es ordering guide model temperature r a nge package descri ption package option 1 ad9260as C40c to +85c 44-lead mqfp s-44 ad9260asrl C40c to +85c 44-lead mqfp s-44 ad9260asz 2 C40c to +85c 44-lead mqfp s-44 ad9260aszrl 2 C40c to +85c 44-lead mqfp s-44 ad9260-eb evaluation boar d 1 s = met r i c qua d f l a t pa ck. 2 z = pb-free part.
ad9260 rev. c | page 44 of 44 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00581C0 C 7/04(c)

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